HANS JURGEN MATTAUSCH

Last Updated :2017/09/01

Affiliations, Positions
Research Institute for Nanodevice and Bio Systems, ., Professor
E-mail
hjmhiroshima-u.ac.jp
Self-introduction
Hans Jürgen Mattausch was born in Hamm, Germany. He received the Dipl. Phys. degree from the University of Dortmund, Dortmund, Germany, and the Dr. rer. nat. degree from the University of Stuttgart, Stuttgart, Germany. In 1982 he joined the Research Laboratories of Siemens AG in Munich, Germany, where he was involved in the development of MOS technology as well as the design of memory and telecommunication circuits. From 1990 he led a research group on MOS-technology based power semicondutor devices, which included device design, modeling and packaging. In 1995 he joined the Siemens Semiconductor Group as Manager of the Department for Product Analysis and Improvement in the Chip Card IC Division. Since 1996 he is with Hiroshima University, Higashi-Hiroshima, Japan, where he is presently a Professor at the Research Institute for Nanodevice and Bio Systems. His main research interest is in VLSI circuit design, associative memories, VLSI implementation of intelligent artificial systems, nanoelectronics, and compact modeling.

Basic Information

Major Professional Backgrounds

  • 1978/01/01, 1978/03/31, Technische Universität Dortmund, Research Assistant
  • 1978/04/01, 1978/10/31, Quelle Versandt Haus, Hardware Designer
  • 1978/11/01, 1981/12/31, Max-Planck-Institut, Researcher
  • 1982/01/01, 1996/09/30, Siemens Central Research, Researcher
  • 1996/10/01, 1998/07/31, Hiroshima University, Associate Professor
  • 1998/08/01, 2007/03/31, Hiroshima University, Professor
  • 2007/04/01, 2008/04/30, Hiroshima University, Vice Director
  • 2008/05/01, Hiroshima University, Research Institute for Nanodevice and Bio Systems, Professor
  • 2008/05/01, 2009/03/31, Hiroshima University, Vice Director, Research Institute for Nanodevice and Bio Systems
  • 2011/04/01, Hiroshima University, Director, HiSIM Research Center

Educational Backgrounds

  • University of Stuttgart, Germany, 1978/11, 1981/05
  • Technical University of Dortmund, Germany, 1972/10, 1977/12

Academic Degrees

  • Doktor der Naturwissenschafter, University of Stuttgart
  • DIPLOM-PHYSIKER, Technical University of Dortmund

Educational Activity

  • Graduate School of Advanced Sciences of Matter:Semiconductor Electronics and Integration Science, Graduate School of Advanced Sciences of Matter:Semiconductor Electronics and Integration Science

In Charge of Primary Major Programs

  • Electronic Devices and Systems
  • Electrical and Electronic Engineering

Research Fields

  • Engineering;Electrical and electronic engineering;Electron device / Electronic equipment

Affiliated Academic Societies

  • Institute of Electronics, Information and Communication Engineers (IEICE), 1999
  • Institute of Electrical and Electronics Engineers (IEEE), 1996

Educational Activity

Course in Charge

  1. 2017, Liberal Arts Education Program1, First Semester, technology and human society
  2. 2017, Undergraduate Education, First Semester, CMOS Logic Circuit Design
  3. 2017, Graduate Education (Master's Program) , First Semester, Special Lecture on Advanced Sciences of Matter
  4. 2017, Graduate Education (Master's Program) , Year, Seminar on Integrated Circuits and Process Engineering
  5. 2017, Graduate Education (Master's Program) , Second Semester, Microprocessor Design
  6. 2017, Graduate Education (Master's Program) , Academic Year, Advanced Study in Semiconductor Electronics and Integration Science I
  7. 2017, Graduate Education (Master's Program) , Year, Advanced Study in Semiconductor Electronics and Integration Science I
  8. 2017, Graduate Education (Master's Program) , Academic Year, Advanced Study in Semiconductor Electronics and Integration Science I
  9. 2017, Graduate Education (Master's Program) , Academic Year, Advanced Study in Semiconductor Electronics and Integration Science I
  10. 2017, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Semiconductor Electronics and Integration ScienceII
  11. 2017, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Semiconductor Electronics and Integration ScienceII
  12. 2017, Graduate Education (Doctoral Program) , Year, Advanced Study in Semiconductor Electronics and Integration ScienceII
  13. 2017, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Semiconductor Electronics and Integration ScienceII
  14. 2017, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Semiconductor Electronics and Integration ScienceII
  15. 2017, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Semiconductor Electronics and Integration ScienceII
  16. 2017, Graduate Education (Doctoral Program) , Intensive, Advanced Study in Semiconductor Electronics and Integration ScienceII

Research Activities

Academic Papers

  1. Compact Modeling of Dynamic MOSFET Degradation Due to Hot-Electrons, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 17(1), 52-58, 20170301
  2. Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures, Sensors, 17(2), 270-283, 20170201
  3. Modeling of Field-Plate Effect on Gallium-Nitride-based High Electron Mobility Transistor for High-Power Applications, IEICE Trans. on Electronics, E100-C(3), 321-328, 20170301
  4. Power-Loss Prediction of High-Voltage SiC-MOSFET Circuits With Compact Model Including Carrier-Trap Influences, IEEE TRANSACTIONS ON POWER ELECTRONICS, 31(6), 4509-4516, 20160601
  5. Physically Based Compact Mobility Model for Organic Thin-Film Transistor, IEEE TRANSACTIONS ON ELECTRON DEVICES, 63(5), 2057-2065, 20160501
  6. Reconfigurable VLSI implementation for learning vector quantization with on-chip learning circuit, JAPANESE JOURNAL OF APPLIED PHYSICS, 55(4), 20160401
  7. Highly flexible nearest-neighbor-search associative memory with integrated k nearest neighbor classifier, configurable parallelism and dual-storage space, JAPANESE JOURNAL OF APPLIED PHYSICS, 55(4), 20160401
  8. Analysis of GaN high electron mobility transistor switching characteristics for high-power applications with HiSIM-GaN compact model, JAPANESE JOURNAL OF APPLIED PHYSICS, 55(4), 20160401
  9. Analysis of printed organic MOSFET characteristics with a focus on the temperature dependence, JAPANESE JOURNAL OF APPLIED PHYSICS, 55(4), 20160401
  10. Actuator-Control Circuit Based on OTFTs and Flow-Rate Estimation for an All-Organic Fluid Pump, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E99A(4), 798-805, 20160401
  11. k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching, IEICE TRANSACTIONS ON ELECTRONICS, E99-C(3), 397-403, 20160301
  12. Efficiency Analysis of SiC-MOSFET-Based Bidirectional Isolated DC/DC Converters, IEICE TRANSACTIONS ON ELECTRONICS, E99C(9), 1065-1070, 20160901
  13. K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 16(4), 405-414, 20160801
  14. A Memory-based Modular Architecture for SOM and LVQ with Dynamic Configuration, IEEE Trans. on Multi-Scale Computing Systems, 2(4), 234-241, 20161001
  15. Mobility model for advanced SOI-MOSFETs including back-gate contribution, JAPANESE JOURNAL OF APPLIED PHYSICS, 54(4), 20150401
  16. VLSI realization of learning vector quantization with hardware/software co-design for different applications, JAPANESE JOURNAL OF APPLIED PHYSICS, 54(4), 20150401
  17. Compact Modeling of the Transient Carrier Trap/Detrap Characteristics in Polysilicon TFTs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 62(3), 862-868, 20150301
  18. Compact Modeling of Injection Enhanced Insulated Gate Bipolar Transistor Valid for Optimization of Switching Frequency, IEICE TRANSACTIONS ON ELECTRONICS, E97C(10), 1021-1027, 20141001
  19. Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 14(3), 818-825, 20140901
  20. A Surface Potential Based Organic Thin-Film Transistor Model for Circuit Simulation Verified With DNTT High Performance Test Devices, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 27(2), 159-168, 20140501
  21. Associative memory architecture for word-parallel smallest Euclidean distance search using distance mapping into clock-number domain, JAPANESE JOURNAL OF APPLIED PHYSICS, 53(4), 20140401
  22. Compact modeling of injection-enhanced insulated-gate bipolar transistor for accurate circuit switching prediction, JAPANESE JOURNAL OF APPLIED PHYSICS, 53(4), 20140401
  23. Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers, IEEE TRANSACTIONS ON ELECTRON DEVICES, 61(2), 255-265, 20140201
  24. Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation, IEICE TRANSACTIONS ON ELECTRONICS, E96C(5), 744-751, 20130501
  25. Analysis and Modeling of Geometry Dependent Thermal Resistance in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, 52(4), 20130401
  26. K-means clustering algorithm for multimedia applications with flexible HW/SW co-design, JOURNAL OF SYSTEMS ARCHITECTURE, 59(3), 155-164, 20130301
  27. HiSIM-IGBT: A Compact Si-IGBT Model for Power Electronic Circuit Design, IEEE TRANSACTIONS ON ELECTRON DEVICES, 60(2), 571-579, 20130201
  28. Modeling of SiC IGBT Turn-Off Behavior Valid for Over 5-kV Circuit Simulation, IEEE TRANSACTIONS ON ELECTRON DEVICES, 60(2), 622-629, 20130201
  29. The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 60(2), 653-661, 20130201
  30. Modeling of the Impurity-Gradient Effect in High-Voltage Laterally Diffused MOSFETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 60(2), 684-690, 20130201
  31. Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions, IEICE TRANSACTIONS ON ELECTRONICS, E96C(10), 1339-1347, 20131001
  32. Compact Modeling of Expansion Effects in LDMOS, IEICE TRANSACTIONS ON ELECTRONICS, E95C(11), 1817-1823, 20121101
  33. Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 47(6), 1448-1459, 20120601
  34. High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 20120401
  35. Compact Thermal-Interaction Model for Dynamic within Chip Temperature Determination by Circuit Simulation, in Proc. Int'l Conf. on Microelectronic Test Structure (ICMTS), 187-190, 20120301
  36. Experimental Extraction of Substrate-Noise Couping between MOSFETs and its Compact Modeling for Circuit Simulation, in Proc. Int'l Conf. on Microelectronic Test Structure (ICMTS), 101-104, 20120301
  37. Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal-Oxide-Semiconductor Technology Including Its Distance Dependences, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 20120401
  38. Unified Reaction-Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(2), 20120201
  39. Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design, IEICE TRANSACTIONS ON ELECTRONICS, E94C(3), 361-367, 20110301
  40. Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics, Jpn. J. Appl. Phys. (JJAP), 50, 1-5, 20110401
  41. An associative memory-based learning model with an efficient hardware implementation in FPGA, EXPERT SYSTEMS WITH APPLICATIONS, 38(4), 3499-3513, 20110401
  42. Analysis of Within-Die Complementary Metal-Oxide-Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM, JAPANESE JOURNAL OF APPLIED PHYSICS, 50(4), 20110401
  43. Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics, JAPANESE JOURNAL OF APPLIED PHYSICS, 50(4), 20110401
  44. Development of the HiSIM-IGBT Model for EV/HV Electric Circuit Simulation, in Proc. the 1st Int'l Electric Vehicle Tech. Conf. (EVTeC), 20110501
  45. Temperature Dependence of Switching Performance in IGBT Circuits and its Compact Modeling, in Proc. the 23rd Int'l Symposium on Power Semicond. Dev. & IC's (ISPSD), 148-151, 20110501
  46. Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type (Invited), NSTI-Nanotech Workshop on Compact Modeling (WCM), 706-709, 20110601
  47. Modeling of the Impurity-Gradient Effect in High-Voltage MOSFETs, NSTI-Nanotech Workshop on Compact Modeling (WCM 2011), 780-783, 20110601
  48. Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices, IEEE Trans. on Electron Devices, 58(7), 2072-2080, 20110701
  49. Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices, IEEE TRANSACTIONS ON ELECTRON DEVICES, 58(7), 2072-2080, 20110701
  50. Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E94D(9), 1742-1754, 20110901
  51. A Scalable Massively Parallel Processor for Real-Time Image Processing, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 46(10), 2363-2373, 20111001
  52. Effect of Carrier Transit Delay on Complementary Metal-Oxide-Semiconductor Switching Performance, JAPANESE JOURNAL OF APPLIED PHYSICS, 49(4), 20100401
  53. Measurement-Based Ring Oscillator Variation Analysis, IEEE DESIGN & TEST OF COMPUTERS, 27(5), 6-13, 20100901
  54. HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET Circuits, IEEE TRANSACTIONS ON ELECTRON DEVICES, 57(10), 2671-2678, 20101001
  55. HiSIM-SOI: A Dynamic Depletion Model Valid for Device and Circuit Optimaization, The 6th International Workshop on Comapact Modeling, 13-16, 20090119
  56. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, Jpn. J. Appl. Phys., 48(4), 04C078, 20090401
  57. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(4), 20090401
  58. Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation, IEICE Trans. on Electronics, E92-C(5), 608-615, 20090501
  59. Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation, IEICE TRANSACTIONS ON ELECTRONICS, E92C(5), 608-615, 20090501
  60. Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the NQS Effect in MOS Varactors, IEICE Trans. on Electronics, E92-C(6), 777-784, 20090601
  61. Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors, IEICE TRANSACTIONS ON ELECTRONICS, E92C(6), 777-784, 20090601
  62. Correlating Microscopic and Macroscopic Variation with Surface-Potential Compact Model, IEEE Electron Device Letters, 30(8), 873-875, 20090801
  63. Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model, IEEE ELECTRON DEVICE LETTERS, 30(8), 873-875, 20090801
  64. Frequency Dependence of Measured Metal Oxide Semiconductor Field-Effect Transistor Distortion Characteristic, Jpn. J. Appl. Phys., 47(4), 2610-2615, 20080401
  65. Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization, Jpn. J. Appl. Phys., 47(4), 2560-2563, 20080401
  66. Laterally diffused metal oxide semiconductor model for device and circuit optimization, JAPANESE JOURNAL OF APPLIED PHYSICS, 47(4), 2560-2563, 20080401
  67. Frequency dependence of measured metal oxide semiconductor field-effect transistor distortion characteristic, JAPANESE JOURNAL OF APPLIED PHYSICS, 47(4), 2610-2615, 20080401
  68. Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization, Jpn. J. Appl. Phys., E91-C, 1379-1381, 20080801
  69. Compact double-gate metal-oxide-semiconductor field effect transistor model for device/circuit optimization, IEICE TRANSACTIONS ON ELECTRONICS, E91C(8), 1379-1381, 20080801
  70. Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor, IEICE Trans. on Electronics, E91-C(9), 1409-1418, 20080901
  71. Integration architecture of content addressable memory and massive-parallel memory-embedded SIMD matrix for versatile multimedia processor, IEICE TRANSACTIONS ON ELECTRONICS, E91C(9), 1409-1418, 20080901
  72. Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations, MATHEMATICS AND COMPUTERS IN SIMULATION, 79(4), 1096-1106, 20081215
  73. Scalable FPGA/ASIC Implementation Architecture for Parallel Table-lookup Coding Using Multi-ported Content Addressable Memory, IEICE Trans. on Information & Systems, E90-D(1), 346-354, 20070101
  74. Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer, IEICE Trans. on Information & Systems, E90-D(1), 334-345, 20070101
  75. Real-time Huffman encoder with pipelined CAM-based data path and code-word-table optimizer, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 334-345, 20070101
  76. Scalable FPGA/ASIC implementation architecture for parallel table-lookup-coding using multi-ported content addressable memory, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 346-354, 20070101
  77. A 2-stage-pipelined 16 Port SRAM with 590 Gbps Random Access Bandwidth and Large Noise Margin, IEICE Electronics Express, 4(2), 21-25, 20070116
  78. A 2-stage-pipelined 16 port SRAM with 590 Gbps random access bandwidth and large noise margin, IEICE ELECTRONICS EXPRESS, 4(2), 21-25, 20070127
  79. Mixed Digital-Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search, Jpn. J. Appl. Phys., 46(4B), 2231-2237, 20070401
  80. Surface-Potential-Based MOS-Varactor Model for RF Applications, Jpn. J. Appl. Phys., 46(4B), 2091-2095, 20070401
  81. Mixed digital-analog associative memory enabling fully-parallel nearest Euclidean distance search, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(4B), 2231-2237, 20070401
  82. Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories, IEICE Trans. on Fundamentals, E90-A(6), 1240-1243, 20070601
  83. Realization of K-Nearest-Matches search capability in fully-parallel associative memories, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A(6), 1240-1243, 20070601
  84. Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor, IEICE Trans. on Information & Systems, E90-D(8), 1312-1215, 20070801
  85. Acceleration of DCT processing with massive-parallel memory-embedded SIMD matrix processor, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(8), 1312-1315, 20070801
  86. Analysis of Technology Variations in Advanced MOSFETs with the Surface-Potential-Based Compact Model HiSIM, Electro-Chemical Society (ECS) Transactions, 11(6), 29-44, 20071101
  87. 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words, IEICE Trans. on Electronics, E90-C(11), 2157-2160, 20071101
  88. Evaluation of Bank based Multi-port Memory Architecture with Blocking Network, Wiley, Systems & Computers in Japan, 37(2), 22-33, 20060201
  89. Evaluation of bank-based multiport memory architecture with blocking network, ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 89(6), 22-33, 20060201
  90. On the validity of Convetional MOSFET Nolineearity Characterization at RF Switching, IEEE Microwave and Wireless components Letters, 16(3), 125-127, 20060301
  91. Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video Segmentation, IEICE Trans. on Information & Systems, E89-D(3), 1299-1302, 20060301
  92. On the validity of conventional MOSFET nonlinearity characterization at RF switching, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 16(3), 125-127, 20060301
  93. Minimum Euclidean Distance Associative Memory Architecture with Fully-Parallel Search Capability, 350-354, 20060401
  94. Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects, IEEE Trans. on Electron Devices, 53(9), 2017-2024, 20060901
  95. A carrier-Times-Delay-Based Nonquasi-Static MOSFET Model for Circuit Simulation and Its Application Harmonic Distortion Analysis, IEEE Transaction on Electron Devices, 53(9), 2025-2034, 20060901
  96. HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation, IEEE Trans. on Electron Devices, 53(9), 1994-2007, 20060901
  97. Performance Evaluation of Superscalar Processor with Multi-Bank Register File and an Implementation Result, WSEAS Transactions on Computer, 9(5), 1993-2000, 20060901
  98. HiSIM2 Circuit Simulation: Solving the Speed versus Accuracy Crisis, IEEE Circuits and Devices Magazine, 22(9), 29-38, 20060901
  99. HiSIM2: Advanced MOSFET model valid for RF circuit simulation, IEEE TRANSACTIONS ON ELECTRON DEVICES, 53(9), 1994-2007, 20060901
  100. Completely surface-potential-based compact model of the-fully depleted SOI-MOSFET including short-channel effects, IEEE TRANSACTIONS ON ELECTRON DEVICES, 53(9), 2017-2024, 20060901
  101. A carrier-transit-delay-based nonquasi-static MOSFET model for circuit simulation and its application to harmonic distortion analysis, IEEE TRANSACTIONS ON ELECTRON DEVICES, 53(9), 2025-2034, 20060901
  102. HiSIM2 circuit simulation - Solving the speed versus accuracy crisis, IEEE CIRCUITS & DEVICES, 22(5), 29-38, 20060901
  103. A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC, IEICE Trans. on Electronics, E89-C(11), 1612-1619, 20061101
  104. A reliability-enhanced TCAM architecture with associated embedded DRAM and ECC, IEICE TRANSACTIONS ON ELECTRONICS, E89C(11), 1612-1619, 20061101
  105. Physics-Based Photodiode Model Enabling Consistent Opto-Electronic Circuit Simulation, 187-190, 20061201
  106. A Cost-Efficient High-Performance Dynamic TCAM With Pipelined Hierarchical Searching and Shift Redundancy Architecture, IEEE Journal of Solid-State Circuits, 40(1), 245-253, 20050101
  107. A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 40(1), 245-253, 20050101
  108. 1/f-noise characteristics in 100nm-MOSFETs and its modeling for circuit simulation, IEICE Trans. on Electronics, E88-C(2), 247-254, 20050201
  109. Evaluation of a Bank-based Multi-port Memory Architecture with Blocking Network, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, J88-A(4), 498-510, 20050401
  110. Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh, IEICE Trans. on Electronics, E88-C(4), 622-629, 20050401
  111. A compact model of the pinch-off region of 100 nm MOSFETs based on the surface-potential, IEICE Trans. on Electronics, E88-C(5), 1079-1086, 20050501
  112. A compact model of the pinch-off region of 100 nm MOSFETs based on the surface-potential, IEICE TRANSACTIONS ON ELECTRONICS, E88C(5), 1079-1086, 20050501
  113. A CAM-based signature-matching co-processor with application-driven power-reduction features, IEICE Trans. on Electronics, E88-C(6), 1332-1342, 20050601
  114. Gate-length and drain-voltage dependence of thermal drain noise in advanced metal-oxide-semiconductor-field-effect transistors, Applied Physics Letters, 87, 092104, 20050824
  115. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors, Systems & Computers in Japan, 36(9), 1-13, 20050901
  116. Pixel-Parallel Digital-CMOS Implementation of Image-Segmentation by Region Growing, IEE Proc. Circuits, Devices & Systems, 152(12), 579-589, 20051201
  117. Distributed against centralized crossbar function for realizing bank-based multiport memories, IEE Electronics Letters, 40(2), 101-103, 20040101
  118. Distributed against centralised crossbar function for realising bank-based multiport memories, ELECTRONICS LETTERS, 40(2), 101-103, 20040122
  119. Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation, E87-D(2), 500-503, 20040201
  120. Distributed-crossbar architecture for area-efficient combined data/instruction caches with multiple ports, IEE Electronics Letters, 40(3), 160-162, 20040201
  121. Non-quasi-static model for MOSFET based on carrier-transit delay, IEE Electronics Letters, 40(4), 276-278, 20040201
  122. A 143MHz, 1.1W, 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture, 208-209, 20040201
  123. 1/f-noise characteristics in 100nm-MOSFETs and its modeling for circuit simulation, IEICE Transactions on Electronics, E88-C(2), 247-254, 20040201
  124. Efficient video-picture segmentation algorithm for cell-network-based digital CMOS implementation, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E87D(2), 500-503, 20040201
  125. Non-quasi-static model for MOSFET based on carrier-transit delay, ELECTRONICS LETTERS, 40(4), 276-278, 20040219
  126. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors, J87-D-I(4), 350-363, 20040401
  127. MOSFET Model HiSIM Based on Surface-Potential Description for Enabling Accurate RF-CMOS Design, Journal of Semiconductor Technology and Science, 4(3), 133-140, 20040901
  128. MOSFET model HiSIM based on surface-potential description for enabling accurate RF-CMOS design, Journal of Semiconductor Technology and Science, 4(3), 133-140, 20040901
  129. Circuit-simulation model of C-gd changes in small-size MOSFETs due to high channel-field gradients, IEICE TRANSACTIONS ON ELECTRONICS, E86C(3), 474-480, 20030301
  130. 100nm-MOSFET Model for Circuit Simulation: Challenges and Solutions, IEICE Trans. on Electronics, E86-C(6), 20030601
  131. Compact Associative-Memory Architecture with Fully-Parallel Search Capability for the Minimum Hamming Distance, IEEE Journal of Solid-State Circuits, 37(2), 218-227, 20020201
  132. Circuit Simulation Models for Coming MOSFET Generations, IEICE Trans. Fundamentals, E85-A(4), 740-748, 20020401
  133. Quantum Effect in Sub-0.1 Micron MOSFET with Pocket Technologies and its Relevance for the On-Current Condition, Jpn. J. Appl. Phys., 41(4), 2359-2362, 20020401
  134. Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal-oxide-semiconductor-field-effect transistors, Appl. Phys. Lett., 80(16), 2994-2996, 20020401
  135. Circuit simulation models for coming MOSFET generations, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A(4), 740-748, 20020401
  136. Quantum effect in sub-0.1 mu m MOSFET with pocket technologies and its relevance for the on-current condition, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 41(4B), 2359-2362, 20020402
  137. Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal-oxide-semiconductor field-effect transistors, APPLIED PHYSICS LETTERS, 80(16), 2994-2996, 20020422
  138. Impurity-Profile-Based Threshold-Voltage Model of Pocket-Implanted MOSFETs for Circuit Simulation, IEEE Trans. on Electron Devices, 49(10), 1783-1789, 20021001
  139. Validity of the mobility universality for scaled MOSFETs down to 100nm gate length, J. Appl. Phys., 92(9), 5228-5232, 20021101
  140. An Architecture for Compact Associative Memories with Deca-ns Nearest-Match Capability up to Large Distances, 170-171, 20010201
  141. Area-efficient multi-port SRAMs for on-chip data-storage with high random-access bandwidth, IEICE Trans. on Electronics, E84-C(3), 410-417, 20010301
  142. Compact central arbiters for memories with multiple ports, Electronics Letters, 37(13), 811-813, 20010601
  143. Physical Modeling of the Reverse-Short-Channel Effect for Circuit Simulation, IEEE Trans. on Electron Devices, 48(10), 2449-2452, 20011001
  144. MOSFET Modeling Gets Physical, IEEE Circuits and Devices Magazine, 17(6), 29-36, 20011101
  145. Super-stable neutral electron traps in nonplanar thermal oxides on monocrystalline silicon, Appl. Phys. Lett., 76(16), 2298-2300, 20000401
  146. Electrical/Thermal Properties of Nonplanar Polyoxides and the Consequent Effects for EEPROM Cell Operation, IEEE Trans. on Electron Devices, 47(6), 1251-1257, 20000601
  147. Hierarchical architecture for area-efficient integrated N-port memories with latency-free multi-gigabit per second access bandwidth, Electronics Letters, 35(17), 1441-1443, 19990801
  148. Fast quadratic increase of multiport-storage-cell area with port number, Electronics Letters, 35(25), 2185-2187, 19991201
  149. Application of Port-Access-Rejection Probability Theory for Integrated N-Port Memory Architecture Optimization, Electronics Letters, 34(9), 861-862, 19980401
  150. Status and Trends of Power Semiconductor Device Models for Circuit Simulation, IEEE Trans. on Power Electronics, 13(3), 452-465, 19980501
  151. A Degradation Mechanism of EEPROM Cell Operational Margins which Remains Undetected by Conventional Quality Assurance, IEEE Electron Device Letters, 19(11), 402-404, 19981101
  152. Localized highly stable electrical passivation of the thermal oxide on nonplanar polycrystalline silicon, Appl. Phys. Lett=, 71(23), 3391-3393, 19971201
  153. Impact of cell geometries and electrothermal effects on IGBT latch-up in 2d-simulation, Simulation of Semiconductor Devices und Processes, 5, 45-48, 19930901
  154. A Memory-Based High-Speed Digital Delay Line with a Large Adjustable Length, IEEE Journal of Solid-State Circuits, 23(1), 105-110, 19880201
  155. A Memory-Based, Arbitrarily Adjustable CMOS Digital Delay Line, Symposium on VLSI Circuits, 21-22, 19870601
  156. A CMOS VLSI Chip for Filtering of TV Pictures in Two Dimensions, IEEE Journal of Solid-State Circuits, 21(5), 797-802, 19861001
  157. Exchange-Correlation Potential for One-Electron Excitations in a Semiconductor, Solid State Communications, 51(1), 23-26, 19840101
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  159. Reactive ion etching of Ta-Silicide/Polysilicon double layers for the fabrication of integrated circuits, Journal of Vacuum Science and Technology, B1(1), 15-22, 19830101
  160. Theory of exchange-correlation effects in the electronic single- and two-particle excitations of covalent crystals, 289-360, 19830101
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Publications such as books

  1. 2010/, /Ju, POWER/HVMOS Devices Compact Modeling, 2010, 6, English, H.J. Mattausch, N. Sadachika, M. Yokomichi, M. Miyake, T. Kajiwara, Y. Oritsuki, T. Sakuda, H. Kikuchihara, U. Feldmann, and M. Miura-Mattausch, ISBN-13: 978-9048130450
  2. 2008/06, The Physics and Modeling of MOSFETs: Surface-Potential Model HiSIM, 2008, 06, English, M. Miura-Mattausch, H.J. Mattausch, T. Ezaki, ISBN13 9789812568649, 350
  3. 1995/09, BRITE-EURAM Project ’’Functional and Reliable CAD for Power Circuit Design’’, Report of Project Results , European Cmmunity, 1995, 09

Invited Lecture, Oral Presentation, Poster Presentation

  1. The HiSIM Compact Models of High-Voltage/Power Semiconductor Devices for Circuit Simulation, MATTAUSCH HANS JUERGEN, T. Umeda, H. Kikuchihara, and M. Miura-Mattausch, International Conference on Solid-State and Integrated-Circuit Technology (ICSICT’2014), 2014/10/30, With Invitation, Guilin, China
  2. Accurate Physical Compact Models of High-Voltage/Power Semiconductor Devices for Efficient Design of Performance-Optimized Circuits and Systems, MATTAUSCH HANS JUERGEN, T. Umeda, H. Kikuchihara, and M. Miura-Mattausch, International Conference on Solid State Devices and Materials (SSDM’2014), 2014/09/10, With Invitation, Tsukuba, Japan
  3. Analysis and Prediction of Device and Circuit Variations with the Compact Surface-Potential Model HiSIM2, MATTAUSCH HANS JUERGEN, A. Yumisaki, A. Kaya, T. Koide, and M. Miura-Mattausch, International Conference on Materials for Advanced Technologies (ICMAT 2011), 2011/05/30, With Invitation, Singapore
  4. HiSIM: The First Complete Drift-Diffusion MOSFET Model for Circuit Simulation, MATTAUSCH HANS JUERGEN, International Conference on Solid-State and Integrated-Circuit Technology (ICSICT''2001), 2011/02, With Invitation, Shanghai, China
  5. The Role of Functional Memories in Parallel Information Processing with Localized and Distributed Systems, MATTAUSCH HANS JUERGEN, K. Johguchi, T. Kumaki, and T. Koide, International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT‘2009), 2009/12/08, With Invitation, Hiroshima, Japan
  6. Surface-Potential-Based Compact Model HiSIM-SOI for Silicon-On-Insulator MOSFETs, MATTAUSCH HANS JUERGEN, N. Sadachika, S. Kusu, K. Ishimura, T. Murakami, M. Ando, and M. Miura-Mattausch, International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES’2009), 2009/06/25, With Invitation, Lodz, Poland
  7. Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model, MATTAUSCH HANS JUERGEN, A. Yumisaki, N. Sadachika, A. Kaya, K. Johguchi, T. Koide, and M. Miura-Mattausch, International Symposium on Diagnostics & Yield (D&Y’2009), 2009/06/22, With Invitation, Warsaw, Poland
  8. HiSIM-HV: A Compact Model for Simulation of High-Voltage-MOSFET Circuits, MATTAUSCH HANS JUERGEN, T. Kajiwara, M. Yokomichi, T. Sakuda, Y. Oritsuki, M. Miyake, N. Sadachika, H. Kikuchihara, U. Feldmann, and M. Miura-Mattausch, International Conference on Solid-State and Integrated-Circuit Technology (ICSICT’2008), 2008/10/22, With Invitation, Bejing, China
  9. The HiSIM Compact Model Family for Integrated Devices Containing a Surface-Potential MOSFET Core, MATTAUSCH HANS JUERGEN, M. Miura-Mattausch, N. Sadachika, M. Miyake, and D. Navarro, International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES’2008), 2008/06/20, With Invitation, Poznan, Poland

Awards

  1. 2005年01月19日, "IEEE Asia and South Pacific Design Automation Conference 2005, University LSI Design Contest, Best Design Paper Award", IEEE Asia and South Pacific Design Automation Conference
  2. 2003年01月24日, "IEEE Asia and South Pacific Design Automation Conference 2003, University LSI Design Contest, Special Feature Award", IEEE Asia and South Pacific Design Automation Conference, A Nearest-Hamming-Distance Search Memory with Fully-Parallel Mixed Digital-Analog Match Circuitry

Patented

  1. Patent, TW:I257589, 2006/07/01
  2. Patent, US:7113416, 2006/09/26
  3. Patent, KR:10-0651340, 2006/11/22
  4. Patent, JP3955953, 2007/05/18
  5. Patent, TW:I297862, 2008/06/11
  6. Patent, EP:1557842, 2008/10/15
  7. Patent, US:7526127, 2009/04/28
  8. Patent, US:7561743, 2009/07/14
  9. Patent, US:7599557, 2009/10/06
  10. Patent, JP4500999, 2010/04/30
  11. Patent, TW:179308, 2003/10/06
  12. Patent, TW:204285, 2004/10/08
  13. Patent, TW:I 226193, 2005/01/01
  14. Patent, JP3689740, 2005/06/24
  15. Patent, JP3742878, 2005/11/25
  16. Patent, EP:1227497, 2006/05/31
  17. Patent, TW:I 258715, 2006/07/21
  18. Patent, JP3861157, 2006/10/06
  19. Patent, US:7203382, 2007/04/10
  20. Patent, US:7298899, 2007/11/20
  21. Patent, EP:1367594, 2008/01/02
  22. Patent, KR:10-0865201, 2008/10/17
  23. Patent, CN:ZL200580005836.X, 2009/10/07
  24. Patent, US:7881525, 2011/02/01
  25. Patent, CN:ZL200910138065.1, 2011/09/28
  26. Patent, TW:135306, 2001/10/23
  27. Patent, TW:137015, 2001/11/12
  28. Patent, KR:0333521, 2002/04/09
  29. Patent, KR:0350525, 2002/08/16
  30. Patent, US:6516392, 2003/02/04
  31. Patent, US:6563163, 2003/05/13
  32. Patent, EP:1039475, 2003/06/25
  33. Patent, KR:0397413, 2003/08/27
  34. Patent, TW:166972, 2003/10/06
  35. Patent, EP:1033722, 2003/12/10
  36. Patent, US:6693815, 2004/02/17
  37. Patent, US:6845429, 2005/01/18
  38. Patent, JP3643864, 2005/02/10
  39. Patent, US:6874068, 2005/03/29
  40. Patent, TW:I 230361, 2005/04/01
  41. Patent, KR:501623, 2005/07/06
  42. Patent, KR:504294, 2005/07/20
  43. Patent, JP3731046, 2005/10/21
  44. Patent, KR:0548883, 2006/01/25
  45. Patent, KR:0549895, 2006/01/31
  46. Patent, JP4742260, 2011/05/20
  47. Patent, JP4892720, 2012/01/06
  48. Patent, JP5224601, 2013/03/22
  49. Patent, US:8587980, 2013/11/19
  50. Patent, JP4208958, 2008/10/31
  51. Patent, JP4229980, 2008/12/12
  52. Patent, JP4303312, 2009/05/01
  53. Patent, JP4427574, 2009/12/18
  54. Patent, US:7853075, 2010/12/14
  55. Patent, US:7860328, 2010/12/28
  56. Patent, JP4743430, 2011/05/20
  57. Patent, US:7957171, 2011/06/07
  58. Patent, JP5035732, 2012/07/13
  59. Patent, JP5103665, 2012/10/12
  60. Patent, US:8331120, 2012/12/11
  61. Patent, JP5223133, 2013/03/22
  62. Patent, JP5261738, 2013/05/10
  63. Patent, JP5390363, 2013/10/18
  64. Patent, US:7746678, 2010/06/29
  65. Patent, KR:505311, 2005/07/25
  66. Patent, TW:I254258, 2006/05/01
  67. Patent, EP00393435B1, Static memory cell
  68. Patent, EP00393434B1, Static memory
  69. Patent, JP11143763A2, Processing circuit device of access conflict
  70. Patent, EP00303815B1, Sense amplifier for a CMOS static memory
  71. Patent, US04893184, Arrangement for DPCM-coding with high data rate
  72. Patent, US04691302, Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable delay of digital signals (1)
  73. Patent, JP02294994A2, Memory hierarchically structured from memory cell
  74. Patent, JP02294992A2, Static memory cell
  75. Patent, US05170375, Hierarchically constructed memory having static memory cells
  76. Patent, EP00213584B1, Circuit arrangement with a memory arranged in a matrix form for variably setting the delay of digital signals (2)
  77. Patent, US04891698, Arrangement for DPCM-coding of video signals
  78. Patent, EP00218918B1, Multidimensional DPCM coder with a high processing speed (1)
  79. Patent, US04860263, Semiconductor memory with random access via two separate inputs/outputs
  80. Patent, JP01067795A2, Read amplifier
  81. Patent, JP01066896A2, Semiconductor memory
  82. Patent, EP00346751B1, Device for the DPCM coding of television signals
  83. Patent, US04748595, Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable delay of digital signals (2)
  84. Patent, 8937828, 2015/01/20
  85. 5800422, 2015/09/04

Social Activities

History as Peer Reviews of Academic Papers

  1. 2014, IEEE Transactions on Electron Devices, Reviewer, 2
  2. 2013, IEEE Transactions on Electron Devices, Reviewer, 1