Michiko Miura

Last Updated :2017/08/01

Affiliations, Positions
HiSIM Research Center, ., Professor (Special Appointment)
E-mail
mmmhiroshima-u.ac.jp

Basic Information

Academic Degrees

  • Dr of Science, Hiroshima University
  • Master of Science, Hiroshima University

Research Keywords

  • transport
  • circuit design
  • model
  • electron
  • device design
  • RF devices
  • Device
  • device model
  • noise

Research Activities

Academic Papers

  1. Universal Relationship between Substrate Current and History Effect in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, 50(4), APR 2011
  2. Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics, JAPANESE JOURNAL OF APPLIED PHYSICS, 50(4), APR 2011
  3. Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices, IEEE TRANSACTIONS ON ELECTRON DEVICES, 58(7), 2072-2080, JUL 2011
  4. Unified Reaction-Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(2), FEB 2012
  5. Dynamic-Carrier-Distribution-Based Compact Modeling of p-i-n Diode Reverse Recovery Effects, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(2), FEB 2012
  6. Compact Modeling of the p-i-n Diode Reverse Recovery Effect Valid for both Low and High Current-Density Conditions, IEICE TRANSACTIONS ON ELECTRONICS, E95C(10), 1682-1688, OCT 2012
  7. Compact Modeling of Expansion Effects in LDMOS, IEICE TRANSACTIONS ON ELECTRONICS, E95C(11), 1817-1823, NOV 2012
  8. The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 60(2), 653-661, FEB 2013
  9. Modeling of the Impurity-Gradient Effect in High-Voltage Laterally Diffused MOSFETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 60(2), 684-690, FEB 2013
  10. Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors, IEICE Trans. Electron., E92-C(6), 777-784, 20090601
  11. Correlating Microscopic and Variation With Surface-Potential Compact Model, IEEE Electron Devices Letters, 30(8), 873-875, 20090801
  12. HiSIM-SOI: A Dynamic Depletion Model Valid for Device and Circuit Optimaization, The 6th International Workshop on Comapact Modeling, 13-16, 20090119
  13. Electro-thermal Simulation for Automotive Power Application using Novel LDMOS Model, The 6th International Workshop on Comapact Modeling, 67-70, 20090119
  14. Analysis and Modeling of p-i-n Photodiode Noise, The 6th International Workshop on Comapact Modeling, 71-74, 20090119
  15. Spatial Distribution Analysis of Self-Heating Effect in High-Voltage MOSFETs, The IEEE Applied Power Electronics Conference and Exposition, 1687-1691, 20090218
  16. HiSIM-SOI: SOI-MOSFET Model for Circuit Simulation Valid also for Device Optimization, NSTI-Nanotech, 550-553, 20090509
  17. Compact Model HiSIM-DG both for Symmetrical and Asymmetrical DG-MOSFET Structures, NSTI-Nanotech, 584-587, 20090509
  18. High-Voltage MOSFET Model Valid for Device Optimization, NSTI-Nanotech, 600-603, 20090509
  19. Correlating Microscopic and Macroscopic Variation with Surface-Potential Compact Model, IEEE Electron Device Letters, 30(8), 873-875, 20090801
  20. Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation, IEICE Trans. on Electronics, E92-C(5), 608-615, 20090501
  21. Surface-Potential-Based Compact Model HiSIM-SOI for Silicon-On-Insulator MOSFETs, 77-81, 20090625
  22. Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model, 20090601
  23. High-Voltage MOSFET Model Valid for Device Optimization, 600-603, 20090515
  24. Modeling of Electron Tunneling in SOI-MOSFET and Its Influence on Device Characteristics, Proc. of 2009 IEEE International SOI Conference, 20091001
  25. Influence of Carrier Transit Delay on CMOS Switching Performance, Proc. of 2009 International Conference on Solid State Devices and Materials, 20091001
  26. Accurate Prediction of Photocurrent Response for High Performance Optoelectric Circuit Simulatio, Proc. of 2009 International Conference on Solid State Devices and Materials, 20091001
  27. Compact model HiSIM-DG valid for independent DG-MOSFETs structures, The 7th International Workshop on Compact Modeling, 20-22, 20100101
  28. Modeling of current for high performance optoelectric circuit, 48-51, 20100101
  29. HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET Circuits, IEEE Transactions on Electron Devices, 57(10), 2671-2678, 20101001
  30. Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design, The Institute of Electronics, Information and Communication Engineers, E94-C(3), 361-367, 20100301
  31. Effect of Carrier Transit delay on Complementary metal-Oxide-Semiconductor Switching Performance, Japanese Journal of Applied Physics, 49, 04DC15-1-04DC15-4, 20100401
  32. Universal relationship between settling time of floating-body SOI MOSFETs and the substrate current in their body-tied counterparts, International Conference on Solid State Devices and Materials, 1013-1014, 20100901
  33. Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices, IEEE Trans. on Electron Devices, 58(7), 2072-2080, 20110701
  34. Universal Relationship between Substrate Current and History Effect in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors, Jpn. J. Appl. Phys. (JJAP), 50, 04DC12, 20110401
  35. Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics, Jpn. J. Appl. Phys. (JJAP), 50, 1-5, 20110401
  36. Compact Thermal-Interaction Model for Dynamic within Chip Temperature Determination by Circuit Simulation, in Proc. Int'l Conf. on Microelectronic Test Structure (ICMTS), 187-190, 20120301
  37. Experimental Extraction of Substrate-Noise Couping between MOSFETs and its Compact Modeling for Circuit Simulation, in Proc. Int'l Conf. on Microelectronic Test Structure (ICMTS), 101-104, 20120301
  38. Reverse-Recovery-Effect Modeling for p-i-n Diodes, The 9th Int'l Workshop on Compact Modeling (IWCM), 25-28, 20120201
  39. Transient History-Effect in SOI-MOSFETs and its Compact Modeling, The 9th Int'l Workshop on Compact Modeling (IWCM), 29-32, 20120201
  40. Modeling of Enhanced 1/f Noise in TFT with Trap Charges, Int'l Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), 171-174, 20110901
  41. Dynamic-Carrier-Distribution-Based Compact Modeling of P-i-N Diode Reverse Recovery Effect, Int'l Conf. on Solid State Devices and Materials (SSDM), 1379-1380, 20110901
  42. Compact Reaction-Diffusion Model for Accurate NBTI Prediction, Int'l Conf. on Solid State Devices and Materials (SSDM), 877-878, 20110901
  43. Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type (Invited), NSTI-Nanotech Workshop on Compact Modeling (WCM), 706-709, 20110601
  44. Modeling of the Impurity-Gradient Effect in High-Voltage MOSFETs, NSTI-Nanotech Workshop on Compact Modeling (WCM 2011), 780-783, 20110601
  45. Development of the HiSIM-IGBT Model for EV/HV Electric Circuit Simulation, in Proc. the 1st Int'l Electric Vehicle Tech. Conf. (EVTeC), 20110501
  46. Temperature Dependence of Switching Performance in IGBT Circuits and its Compact Modeling, in Proc. the 23rd Int'l Symposium on Power Semicond. Dev. & IC's (ISPSD), 148-151, 20110501
  47. Analysis and Further Improvements of the Drain-Resistance Modeling in HiSIM_HV, pp. 7-11, 20120901
  48. Analysis and Modeling of Geometry Dependent Thermal Resistances in MOSFETs, Proc. SSDM, pp. 104-105, 20120901
  49. Characterization of Time Dependent Carrier Trapping In Poly-Crystalline TFTs and Its Accurate Modeling for Circuit Simulation, Proc. SISPAD 2012, pp. 71-74, 20120901
  50. Compact Modeling of Floating-Base Effect in IGBT Based on Potential Modification by Accumulated Charge, Proc. SSDM, pp. 1239-1240, 20120901
  51. Compact Modeling of the Punch-Through Effect in SiC-IGBT for 6.6kV Switching Operation with Improved Performance, Proc. ECSCRM, MoP-86, 20120901
  52. Compact physics-based modeling of semiconductor devices for circuit, Proc. 2013 German Physical Society (DPG) Spring Meeting, HL 47.1, 20130301
  53. Development of Predictive Model and Circuit Simulation Methodology for Negative Bias Temperature Instability Effects, Proc. SISPAD, pp. 213 - 216, 20120901
  54. Development of Unified Predictive NBTI Model and its Application for Circuit Aging Simulation, pp. 47-50, 20130101
  55. Floating-Base Effect Modeling for IGBT Structure Using Potential Modification, pp. 13-16, 20130101
  56. HiSIM-SOTB: A Compact Model for SOI-MOSFET with Ultra-Thin Si-Layer and BOX, NSTI-Nanotech 2012, pp. 792-795, 20120601
  57. Modeling of Chain-History Effect based on HiSIM-SOI, NSTI-Nanotech 2012, pp. 788-791, 20120601
  58. Modeling of DMOS Device for High-Voltage applications Based on 2D Current Flow, NSTI-Nanotech 2012, pp. 752-755, 20120601
  59. Modeling of the Impurity-Gradient Effect in High-Voltage Laterally-Diffused MOSFETs, Proc. SSDM, E95-C, pp. 474-475, 20120901
  60. Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation, NSTI-Nanotech 2012, pp. 748-751, 20120601
  61. Specific Features of SiC-IGBT with 13kV Switching, Proc. the 24th Int'l Symposium on Power Semicond. Dev. & IC's, pp. 261-264, 20120601
  62. Surface Potential Based Modeling of Organic Thin-Film Transistor for Circuit Simulation, pp. 27-32, 20130101
  63. Modeling of Subthreshold Swing and Analysis of Short-Channel Effects in Double-Gate Metal Oxide Semiconductor Field-Effect Transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(4), APR 2009
  64. Capability of Electrothermal Simulation for Automotive Power Application Using Novel Laterally Diffused Metal Oxide Semiconductor Model, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(4), APR 2009
  65. A PN Junction-Current Model for Advanced MOSFET Technologies, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E92A(4), 983-989, APR 2009
  66. Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation, IEICE TRANSACTIONS ON ELECTRONICS, E92C(5), 608-615, MAY 2009
  67. Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors, IEICE TRANSACTIONS ON ELECTRONICS, E92C(6), 777-784, JUN 2009
  68. Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model, IEEE ELECTRON DEVICE LETTERS, 30(8), 873-875, AUG 2009
  69. A Bulk-Current Model for Advanced MOSFET Technologies Without Binning: Substrate Current and Fowler-Nordheim Current, IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, 5(1), 96-104, JAN 2010
  70. Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design, IEICE TRANSACTIONS ON ELECTRONICS, E94C(3), 361-367, MAR 2011
  71. Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation, IEICE TRANSACTIONS ON ELECTRONICS, E96C(5), 744-751, MAY 2013
  72. Analysis and Modeling of Geometry Dependent Thermal Resistance in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, 52(4), APR 2013
  73. Compact Modeling of Floating-Base Effect in Injection-Enhanced Insulated-Gate Bipolar Transistor Based on Potential Modification by Accumulated Charge, JAPANESE JOURNAL OF APPLIED PHYSICS, 52(4), APR 2013
  74. Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions, IEICE TRANSACTIONS ON ELECTRONICS, E96C(10), 1339-1347, OCT 2013
  75. Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers, IEEE TRANSACTIONS ON ELECTRON DEVICES, 61(2), 255-265, FEB 2014
  76. A Surface Potential Based Organic Thin-Film Transistor Model for Circuit Simulation Verified With DNTT High Performance Test Devices, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 27(2), 159-168, MAY 2014
  77. Compact modeling of injection-enhanced insulated-gate bipolar transistor for accurate circuit switching prediction, JAPANESE JOURNAL OF APPLIED PHYSICS, 53(4), APR 2014
  78. Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 14(3), 818-825, SEP 2014
  79. Compact Modeling of Injection Enhanced Insulated Gate Bipolar Transistor Valid for Optimization of Switching Frequency, IEICE TRANSACTIONS ON ELECTRONICS, E97C(10), 1021-1027, OCT 2014
  80. Degradation of 4H-SiC IGBT threshold characteristics due to SiC/SiO2 interface defects, SOLID-STATE ELECTRONICS, 101, 126-130, NOV 2014
  81. Compact Modeling of the Transient Carrier Trap/Detrap Characteristics in Polysilicon TFTs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 62(3), 862-868, MAR 2015
  82. Mobility model for advanced SOI-MOSFETs including back-gate contribution, JAPANESE JOURNAL OF APPLIED PHYSICS, 54(4), APR 2015
  83. Switching characteristics of a 4H-SiC insulated-gate bipolar transistor with interface defects up to the nonquasi-static regime, JAPANESE JOURNAL OF APPLIED PHYSICS, 54(4), APR 2015
  84. Power-Loss Prediction of High-Voltage SiC-MOSFET Circuits With Compact Model Including Carrier-Trap Influences, IEEE TRANSACTIONS ON POWER ELECTRONICS, 31(6), 4509-4516, JUN 2016

Awards

  1. 2009年11月19日, Avon Women Award, Avon Women Cultural Center
  2. 2008年, Hiroshima University President Award, Hiroshima University
  3. 2009年04月, Minister of Education and Science Award, Research Field, Ministry of Education and Science, キャリア応答の解明と回路モデル応用の解明と回路モデル応用への研究
  4. 2008年10月, Hokokai Award, Hattori Hokokai Foundation, デバイス物理の解明とこのモデル化
  5. 2008年12月, NISTEP Researcer Award, National Institute of Science and Technology Policy, 半導体超微細化時代に適合する技術的に卓越したトランジスタモデルの開発と国際標準化の獲得
  6. 1998年02月, Best Paper Award, Asia and South Pacific Data Automation Conference 学会委員長, "Concurrent Technology, Device, and Circuit Development for EEPROMs"
  7. 2001年01月, Best Paper Award, Asia and South Pacific Data Automation Conference 学会委員長, Correlation Method of Circuit-Performance and Technology Fluctuations for Improved Design Relaibility
  8. 2006年11月, THE GRADE OF FELLOW, IEEE会長
  9. 2012年11月03日, Medal of Honour with Purple Ribbon, Government of Japan