三浦 道子Michiko Miura

Last Updated :2017/08/01

所属・職名
HiSIM研究センター HiSIM研究センター 特任教授
メールアドレス
mmmhiroshima-u.ac.jp

基本情報

学位

  • 理学博士 (広島大学)
  • 理学修士 (広島大学)

研究キーワード

  • 輸送
  • 回路設計
  • モデル
  • 電子
  • デバイス設計
  • RFデバイス
  • デバイス
  • デバイスモデル
  • ノイズ

研究活動

学術論文(★は代表的な論文)

  1. Universal Relationship between Substrate Current and History Effect in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, 50巻, 4号, APR 2011
  2. Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics, JAPANESE JOURNAL OF APPLIED PHYSICS, 50巻, 4号, APR 2011
  3. Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices, IEEE TRANSACTIONS ON ELECTRON DEVICES, 58巻, 7号, pp.2072-pp.2080, JUL 2011
  4. Unified Reaction-Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect, JAPANESE JOURNAL OF APPLIED PHYSICS, 51巻, 2号, FEB 2012
  5. Dynamic-Carrier-Distribution-Based Compact Modeling of p-i-n Diode Reverse Recovery Effects, JAPANESE JOURNAL OF APPLIED PHYSICS, 51巻, 2号, FEB 2012
  6. Compact Modeling of the p-i-n Diode Reverse Recovery Effect Valid for both Low and High Current-Density Conditions, IEICE TRANSACTIONS ON ELECTRONICS, E95C巻, 10号, pp.1682-pp.1688, OCT 2012
  7. Compact Modeling of Expansion Effects in LDMOS, IEICE TRANSACTIONS ON ELECTRONICS, E95C巻, 11号, pp.1817-pp.1823, NOV 2012
  8. The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 60巻, 2号, pp.653-pp.661, FEB 2013
  9. Modeling of the Impurity-Gradient Effect in High-Voltage Laterally Diffused MOSFETs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 60巻, 2号, pp.684-pp.690, FEB 2013
  10. Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors, IEICE Trans. Electron., E92-C巻, 6号, pp.777-pp.784, 20090601
  11. Correlating Microscopic and Variation With Surface-Potential Compact Model, IEEE Electron Devices Letters, 30巻, 8号, pp.873-pp.875, 20090801
  12. HiSIM-SOI: A Dynamic Depletion Model Valid for Device and Circuit Optimaization, The 6th International Workshop on Comapact Modeling, pp.13-pp.16, 20090119
  13. Electro-thermal Simulation for Automotive Power Application using Novel LDMOS Model, The 6th International Workshop on Comapact Modeling, pp.67-pp.70, 20090119
  14. Analysis and Modeling of p-i-n Photodiode Noise, The 6th International Workshop on Comapact Modeling, pp.71-pp.74, 20090119
  15. Spatial Distribution Analysis of Self-Heating Effect in High-Voltage MOSFETs, The IEEE Applied Power Electronics Conference and Exposition, pp.1687-pp.1691, 20090218
  16. 高耐圧MOSFET特性のモデル化と回路シュミレータへの組み込み, 第22回回路とシステム軽井沢ワークショップ, pp.37-pp.41, 20090421
  17. HiSIM-SOI: SOI-MOSFET Model for Circuit Simulation Valid also for Device Optimization, NSTI-Nanotech, pp.550-pp.553, 20090509
  18. Compact Model HiSIM-DG both for Symmetrical and Asymmetrical DG-MOSFET Structures, NSTI-Nanotech, pp.584-pp.587, 20090509
  19. High-Voltage MOSFET Model Valid for Device Optimization, NSTI-Nanotech, pp.600-pp.603, 20090509
  20. Correlating Microscopic and Macroscopic Variation with Surface-Potential Compact Model, IEEE Electron Device Letters, 30巻, 8号, pp.873-pp.875, 20090801
  21. Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation, IEICE Trans. on Electronics, E92-C巻, 5号, pp.608-pp.615, 20090501
  22. Surface-Potential-Based Compact Model HiSIM-SOI for Silicon-On-Insulator MOSFETs, Proceedings of the 16th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES’2009), pp.77-pp.81, 20090625
  23. Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model, Proceedings of the 8th International Symposium on Diagnostics & Yield (D&Y’2009), 20090601
  24. High-Voltage MOSFET Model Valid for Device Optimization, Proceedings of the 2009 NIST Nanotechnology Conference and Trade Show (NIST-Nanotech ’2009), pp.600-pp.603, 20090515
  25. p-i-nフォトダイオードにおける光入力応答の測定及びモデル化, 第70回応用物理学会学術講演会予稿集, 20091001
  26. TFTにおけるGrain BoundaryのThermal Noiseへの影響, 第70回応用物理学会学術講演会予稿集, 20091001
  27. Drift-Diffusionを考慮した完全対称モデルの実現, 第70回応用物理学会学術講演会, 20090901
  28. TFTで特徴的に誘起される1/f noiseの解析, 第70回応用物理学会学術講演会予稿集, 20090901
  29. Modeling of Electron Tunneling in SOI-MOSFET and Its Influence on Device Characteristics, Proc. of 2009 IEEE International SOI Conference, 20091001
  30. Influence of Carrier Transit Delay on CMOS Switching Performance, Proc. of 2009 International Conference on Solid State Devices and Materials, 20091001
  31. Accurate Prediction of Photocurrent Response for High Performance Optoelectric Circuit Simulatio, Proc. of 2009 International Conference on Solid State Devices and Materials, 20091001
  32. MOSFETコンパクトモデルと今後の展開―バルクMOSFETからマルチゲートMOSFETに向けて―, (社)電子情報通信学会信学技報, 109巻, 278号, pp.2-pp.7, 20091101
  33. 回路シミュレーション用IGBTモデル“HiSIM-IGBT”, (社)電子情報通信学会信学技報, 109巻, 278号, pp.23-pp.27, 20091101
  34. Compact model HiSIM-DG valid for independent DG-MOSFETs structures, The 7th International Workshop on Compact Modeling, pp.20-pp.22, 20100101
  35. Modeling of current for high performance optoelectric circuit, pp.48-pp.51, 20100101
  36. HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET Circuits, IEEE Transactions on Electron Devices, 57巻, 10号, pp.2671-pp.2678, 20101001
  37. Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design, The Institute of Electronics, Information and Communication Engineers, E94-C巻, 3号, pp.361-pp.367, 20100301
  38. Effect of Carrier Transit delay on Complementary metal-Oxide-Semiconductor Switching Performance, Japanese Journal of Applied Physics, 49巻, pp.04DC15-1-04DC15-4, 20100401
  39. Universal relationship between settling time of floating-body SOI MOSFETs and the substrate current in their body-tied counterparts, International Conference on Solid State Devices and Materials, pp.1013-pp.1014, 20100901
  40. Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices, IEEE Trans. on Electron Devices, 58巻, 7号, pp.2072-pp.2080, 20110701
  41. Universal Relationship between Substrate Current and History Effect in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors, Jpn. J. Appl. Phys. (JJAP), 50巻, pp.04DC12, 20110401
  42. Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics, Jpn. J. Appl. Phys. (JJAP), 50巻, pp.1-pp.5, 20110401
  43. Compact Thermal-Interaction Model for Dynamic within Chip Temperature Determination by Circuit Simulation, in Proc. Int'l Conf. on Microelectronic Test Structure (ICMTS), pp.187-pp.190, 20120301
  44. Experimental Extraction of Substrate-Noise Couping between MOSFETs and its Compact Modeling for Circuit Simulation, in Proc. Int'l Conf. on Microelectronic Test Structure (ICMTS), pp.101-pp.104, 20120301
  45. Reverse-Recovery-Effect Modeling for p-i-n Diodes, The 9th Int'l Workshop on Compact Modeling (IWCM), pp.25-pp.28, 20120201
  46. Transient History-Effect in SOI-MOSFETs and its Compact Modeling, The 9th Int'l Workshop on Compact Modeling (IWCM), pp.29-pp.32, 20120201
  47. Modeling of Enhanced 1/f Noise in TFT with Trap Charges, Int'l Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), pp.171-pp.174, 20110901
  48. Dynamic-Carrier-Distribution-Based Compact Modeling of P-i-N Diode Reverse Recovery Effect, Int'l Conf. on Solid State Devices and Materials (SSDM), pp.1379-pp.1380, 20110901
  49. Compact Reaction-Diffusion Model for Accurate NBTI Prediction, Int'l Conf. on Solid State Devices and Materials (SSDM), pp.877-pp.878, 20110901
  50. Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type (Invited), NSTI-Nanotech Workshop on Compact Modeling (WCM), pp.706-pp.709, 20110601
  51. Modeling of the Impurity-Gradient Effect in High-Voltage MOSFETs, NSTI-Nanotech Workshop on Compact Modeling (WCM 2011), pp.780-pp.783, 20110601
  52. Development of the HiSIM-IGBT Model for EV/HV Electric Circuit Simulation, in Proc. the 1st Int'l Electric Vehicle Tech. Conf. (EVTeC), 20110501
  53. Temperature Dependence of Switching Performance in IGBT Circuits and its Compact Modeling, in Proc. the 23rd Int'l Symposium on Power Semicond. Dev. & IC's (ISPSD), pp.148-pp.151, 20110501
  54. Analysis and Further Improvements of the Drain-Resistance Modeling in HiSIM_HV, pp.pp. 7-11, 20120901
  55. Analysis and Modeling of Geometry Dependent Thermal Resistances in MOSFETs, Proc. SSDM, pp.pp. 104-105, 20120901
  56. Characterization of Time Dependent Carrier Trapping In Poly-Crystalline TFTs and Its Accurate Modeling for Circuit Simulation, Proc. SISPAD 2012, pp.pp. 71-74, 20120901
  57. Compact Modeling of Floating-Base Effect in IGBT Based on Potential Modification by Accumulated Charge, Proc. SSDM, pp.pp. 1239-1240, 20120901
  58. Compact Modeling of the Punch-Through Effect in SiC-IGBT for 6.6kV Switching Operation with Improved Performance, Proc. ECSCRM, pp.MoP-86, 20120901
  59. Compact physics-based modeling of semiconductor devices for circuit, Proc. 2013 German Physical Society (DPG) Spring Meeting, pp.HL 47.1, 20130301
  60. Development of Predictive Model and Circuit Simulation Methodology for Negative Bias Temperature Instability Effects, Proc. SISPAD, pp.pp. 213 - 216, 20120901
  61. Development of Unified Predictive NBTI Model and its Application for Circuit Aging Simulation, pp.pp. 47-50, 20130101
  62. Floating-Base Effect Modeling for IGBT Structure Using Potential Modification, pp.pp. 13-16, 20130101
  63. HiSIM-SOTB: A Compact Model for SOI-MOSFET with Ultra-Thin Si-Layer and BOX, NSTI-Nanotech 2012, pp.pp. 792-795, 20120601
  64. Modeling of Chain-History Effect based on HiSIM-SOI, NSTI-Nanotech 2012, pp.pp. 788-791, 20120601
  65. Modeling of DMOS Device for High-Voltage applications Based on 2D Current Flow, NSTI-Nanotech 2012, pp.pp. 752-755, 20120601
  66. Modeling of the Impurity-Gradient Effect in High-Voltage Laterally-Diffused MOSFETs, Proc. SSDM, E95-C巻, pp.pp. 474-475, 20120901
  67. Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation, NSTI-Nanotech 2012, pp.pp. 748-751, 20120601
  68. Specific Features of SiC-IGBT with 13kV Switching, Proc. the 24th Int'l Symposium on Power Semicond. Dev. & IC's, pp.pp. 261-264, 20120601
  69. Surface Potential Based Modeling of Organic Thin-Film Transistor for Circuit Simulation, pp.pp. 27-32, 20130101
  70. 半導体デバイスのコンパクトモデル:現状と将来展望, 第60回応用物理学会春季学術講演会, pp.27a-G10-1, 20130301
  71. Modeling of Subthreshold Swing and Analysis of Short-Channel Effects in Double-Gate Metal Oxide Semiconductor Field-Effect Transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, 48巻, 4号, APR 2009
  72. Capability of Electrothermal Simulation for Automotive Power Application Using Novel Laterally Diffused Metal Oxide Semiconductor Model, JAPANESE JOURNAL OF APPLIED PHYSICS, 48巻, 4号, APR 2009
  73. A PN Junction-Current Model for Advanced MOSFET Technologies, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E92A巻, 4号, pp.983-pp.989, APR 2009
  74. Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation, IEICE TRANSACTIONS ON ELECTRONICS, E92C巻, 5号, pp.608-pp.615, MAY 2009
  75. Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors, IEICE TRANSACTIONS ON ELECTRONICS, E92C巻, 6号, pp.777-pp.784, JUN 2009
  76. Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model, IEEE ELECTRON DEVICE LETTERS, 30巻, 8号, pp.873-pp.875, AUG 2009
  77. A Bulk-Current Model for Advanced MOSFET Technologies Without Binning: Substrate Current and Fowler-Nordheim Current, IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, 5巻, 1号, pp.96-pp.104, JAN 2010
  78. Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design, IEICE TRANSACTIONS ON ELECTRONICS, E94C巻, 3号, pp.361-pp.367, MAR 2011
  79. Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation, IEICE TRANSACTIONS ON ELECTRONICS, E96C巻, 5号, pp.744-pp.751, MAY 2013
  80. Analysis and Modeling of Geometry Dependent Thermal Resistance in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, 52巻, 4号, APR 2013
  81. Compact Modeling of Floating-Base Effect in Injection-Enhanced Insulated-Gate Bipolar Transistor Based on Potential Modification by Accumulated Charge, JAPANESE JOURNAL OF APPLIED PHYSICS, 52巻, 4号, APR 2013
  82. Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions, IEICE TRANSACTIONS ON ELECTRONICS, E96C巻, 10号, pp.1339-pp.1347, OCT 2013
  83. Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers, IEEE TRANSACTIONS ON ELECTRON DEVICES, 61巻, 2号, pp.255-pp.265, FEB 2014
  84. A Surface Potential Based Organic Thin-Film Transistor Model for Circuit Simulation Verified With DNTT High Performance Test Devices, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 27巻, 2号, pp.159-pp.168, MAY 2014
  85. Compact modeling of injection-enhanced insulated-gate bipolar transistor for accurate circuit switching prediction, JAPANESE JOURNAL OF APPLIED PHYSICS, 53巻, 4号, APR 2014
  86. Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 14巻, 3号, pp.818-pp.825, SEP 2014
  87. Compact Modeling of Injection Enhanced Insulated Gate Bipolar Transistor Valid for Optimization of Switching Frequency, IEICE TRANSACTIONS ON ELECTRONICS, E97C巻, 10号, pp.1021-pp.1027, OCT 2014
  88. Degradation of 4H-SiC IGBT threshold characteristics due to SiC/SiO2 interface defects, SOLID-STATE ELECTRONICS, 101巻, pp.126-pp.130, NOV 2014
  89. Compact Modeling of the Transient Carrier Trap/Detrap Characteristics in Polysilicon TFTs, IEEE TRANSACTIONS ON ELECTRON DEVICES, 62巻, 3号, pp.862-pp.868, MAR 2015
  90. Mobility model for advanced SOI-MOSFETs including back-gate contribution, JAPANESE JOURNAL OF APPLIED PHYSICS, 54巻, 4号, APR 2015
  91. Switching characteristics of a 4H-SiC insulated-gate bipolar transistor with interface defects up to the nonquasi-static regime, JAPANESE JOURNAL OF APPLIED PHYSICS, 54巻, 4号, APR 2015
  92. Power-Loss Prediction of High-Voltage SiC-MOSFET Circuits With Compact Model Including Carrier-Trap Influences, IEEE TRANSACTIONS ON POWER ELECTRONICS, 31巻, 6号, pp.4509-pp.4516, JUN 2016

受賞

  1. 2009年11月19日, 2009エイボン女性年度賞 エイボン女性賞, エイボン女性文化センター
  2. 2008年, 第7回広島大学学長表彰, 広島大学学長
  3. 2009年04月, 平成21年度科学技術分野の文部科学大臣表彰科学技術賞(研究部門), 文部科学大臣, キャリア応答の解明と回路モデル応用の解明と回路モデル応用への研究
  4. 2008年10月, 報公賞, 財団法人服部報公会, デバイス物理の解明とこのモデル化
  5. 2008年12月, ナイスステップな研究者, 文部科学省科学技術政策研究所, 半導体超微細化時代に適合する技術的に卓越したトランジスタモデルの開発と国際標準化の獲得
  6. 1998年02月, Best Paper Award, Asia and South Pacific Data Automation Conference 学会委員長, "Concurrent Technology, Device, and Circuit Development for EEPROMs"
  7. 2001年01月, Best Paper Award, Asia and South Pacific Data Automation Conference 学会委員長, Correlation Method of Circuit-Performance and Technology Fluctuations for Improved Design Relaibility
  8. 2009年11月, 第66回中国文化賞
  9. 2006年11月, THE GRADE OF FELLOW, IEEE会長
  10. 2012年11月03日, 紫綬褒章, 日本国