DONDEE SERVEZA NAVARRO

Last Updated :2021/05/10

Affiliations, Positions
HiSIM Research Center, Associate Professor
Web Site
Self-introduction
My research is focused on the development of compact models for semiconductor devices such as MOSFET, high-voltage MOS (HVMOS), super-junction (SJMOS) and IGBT. The compact models are used in simulating circuits to predict circuit performance, and to aid in circuit design optimization. To support the development of compact models, my work also involves device simulations using TCAD software to determine the physical phenomena behind the operation of the devices. On-wafer measurements of the DC and AC characteristics of devices are also performed. Our group in HiSIM Research Center has developed standard compact models for MOSFET, HVMOS, SOI and SOTB, which are used in the electronics industry. We are also developing models for high-voltage and high-power devices employing SiC material.

Basic Information

Educational Backgrounds

  • University of the Philippines, College of Science, Applied Physics, Philippines, 1992/06, 1997/04
  • Hiroshima University, Graduate School of Advanced Sciences of Matter , Japan, 2002/04, 2004/03
  • Hiroshima University, Graduate School of Advanced Sciences of Matter , Japan, 2004/04, 2006/09

Academic Degrees

  • Master of Engineering, Hiroshima University
  • Ph.D., Hiroshima University

Research Fields

  • Engineering;Electrical and electronic engineering;Electron device / Electronic equipment

Research Keywords

  • Semiconductor device modeling, TCAD, Spice, Verilog-A, Power devices, Power electronic circuits, Parameter extraction

Affiliated Academic Societies

  • IEEE (Institute of Electrical and Electronics Engineers)

Research Activities

Academic Papers

  1. Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 27(7), 1675-1684, 201907
  2. Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs, IEICE TRANSACTIONS ON ELECTRONICS, E102C(6), 487-494, 201906
  3. Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs, IEICE Transactions on Electronics, 102-C(6), 201906
  4. Potential-Based Modeling of Depletion-Mode MOSFET Applicable for Structural Variations, IEEE TRANSACTIONS ON ELECTRON DEVICES, 66(1), 52-59, 201901
  5. Modeling of Carrier Trapping and Its Impact on Switching Performance, IEEE Journal of the Electron Devices Society, 6, 1056-1063, 201808
  6. Compact modeling of SiC Schottky barrier diode and its extension to junction barrier Schottky diode, JAPANESE JOURNAL OF APPLIED PHYSICS, 57(4), 201804
  7. Modeling of Carrier Trapping and Its Impact on Switching Performance, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 6(1), 1056-1063, 2018
  8. Walking robot movement on non-smooth surface controlled by pressure sensor, Advanced Materials Letters, 9(2), 123-127, 201802
  9. Compact modeling of dynamic trap density evolution for predicting circuit performance aging, MICROELECTRONICS RELIABILITY, 80, 164-175, 201801
  10. Enhanced Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor in the presence of interface traps, JAPANESE JOURNAL OF APPLIED PHYSICS, 56(4), 201704
  11. Investigation of 4H-SiC IGBT Turn-off Performance for Achieving Low Power Loss, JAPANESE JOURNAL OF APPLIED PHYSICS, 55, 201603
  12. Switching Characteristics of a 4H-SiC IGBT with Interface Defects Up to the Nonquasi-Static Regime, JAPANESE JOURNAL OF APPLIED PHYSICS, 54, 2015
  13. Degradation of 4H-SiC IGBT threshold characteristics due to SiC/SiO2 interface defects, SOLID-STATE ELECTRONICS, 101, 201411
  14. HiSIM-IGBT: A Compact Si-IGBT Model for Power Electronic Circuit Design, IEEE TRANSACTIONS ON ELECTRON DEVICES, 62(2), 201302
  15. A Sequential Model Parameter Extraction Technique for Physics-Based IGBT Compact Models, IEEE TRANS ON ELECTRON DEVICES, 60(2), 201302
  16. High frequency response of p-i-n photodiodes analyzed by an analytical model in Fourier space, JAPANESE JOURNAL OF APPLIED PHYSICS, 96(7), 201010
  17. A GIDL-Current Model for Advanced MOSFET Technologies without Binning, IPSJ Transactions on System LSI Design Methodology, 2, 200902
  18. A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2, IEEJ Transactions on Electrical and Electronic Engineering, 3(1), 200801
  19. Surface-Potential-Based Metal-Oxide Silicon-Varactor Model for RF Applications, JAPANESE JOURNAL OF APPLIED PHYSICS, 46(4B), 200704
  20. Shot Noise Modeling in Metal-Oxide-Semiconductor Field Effect Transistors under Sub-Threshold Condition, IEICE Trans. Electronics, E90-C(4), 200704
  21. HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation, IEEE Trans. Electron Devices, 53(9), 200609
  22. Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects, IEEE Trans. Electron Devices, 53(9), 200609
  23. On the Validity of Conventional MOSFET Nonlinearity Characterization at RF Switc, IEEE Microwave and Wireless Components Letters, 16(3), 200603
  24. A Carrier-Transit-Delay-Based Nonquasi-Static MOSFET Model for Circuit Simulation and Its Application Harmonic Distortion Analysis, IEEE Trans. Electron Devices, 53(9), 200609
  25. HiSIM2 Ciruit Simulation, IEEE Circuits & Devices M, 22(5), 200609
  26. Gate-length and drain-voltage dependence of thermal drain noise in advanced metal-oxide-semiconductor-field-effect transistors, Appl. Phys. Letters, 87, 200508
  27. A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential, IEICE Trans. Electronics, E88-C(5), 200505
  28. Carrier Transport Model for Lateral p-i-n Photodiode in High-Frequency Operation, JAPANESE JOURNAL OF APPLIED PHYSICS, 44(4B), 200504
  29. Non-quasi-static model for MOSFET based on carrier-transit delay, IEE Electronics Letters, 40(4), 200402
  30. Limit of validity of the drift-diffusion approximation for simulation of photodiode characteristics, Appl. Phys. Letters, 84(8), 200402
  31. Circuit-Simulation Model of Cgd Changes in Small-Size MOSFETs Due to High Channel-Field Gradients, IEICE TRANSACTIONS ON ELECTRONICS, E86-C(3), 200303
  32. Potential-Based Modeling of Depletion-Mode MOSFET Applicable for Structural Variations, IEEE Trans. on Electron Devices, 66(1), 52-59, 201901
  33. Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model, IEICE TRANSACTIONS ON ELECTRONICS, E103C(3), 119-126, 202003
  34. Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation, IEEE ACCESS, 9, 23786-23794, 2021

Invited Lecture, Oral Presentation, Poster Presentation

  1. Predictive Compact Modeling of Abnormal LDMOS Characteristics Due to Overlap-Length Modification, 2. T. Iizuka, D. Navarro, M. Miura-Mattausch, H. Kikuchihara, H. J. Mattausch and D. N. Rus, 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Without Invitation, English
  2. Compact Modeling and Circuit Simulation for High-Power Devices, D. Navarro and T. Iizuka, International Conf. on Solid State Devices and Materials (SSDM), 2019/09, With Invitation, English
  3. Compact Modeling for Leading-Edge Thin-Layer MOSFETs with Additional Applicability in Device Optimization toward Suppressed Short-Channel Effects, F. Herrera, Y. Hirano, T. Iizuka, M. Miura-Mattausch, H. Kikuchihara, D. Navarro, H.J. Mattausch, and A. Ito, Electron Devices Technology and Manufacturing (EDTM), 2019/03, Without Invitation, English
  4. Analysis of Embedded-Diode Performance in MOSFET under Switching Condition, 22. T. Yamamoto, Y. Fukunaga, D. Ikoma, M. Miura-Mattausch, D. Navarro, H. J. Mattausch, nternational Symposium on Devices, Circuits and Systems (ISDCS), 2019/03, Without Invitation, English
  5. Recent Challenges in Compact Modeling of Short-Channel Effect for Leading-Edge Types of MOSFETs, F. Herrera, Y. Hirano, T. Iizuka, M. Miura-Mattausch, H. Kikuchihara, D. Navarro, H Mattausch, and A. Ito, 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT, 2018/10, Without Invitation, English
  6. Self-Controlled Walking Robot with Gyro Sensor Network for Stable Movement on Non-Smooth Surface, S. Dutta, T. K. Maiti, Y. Ochi, M. Miura-Mattausch, S. Bhattacharya, D. Navarro, N. Yorino, H. Jürgen Mattausch, IEEE International Conference on Simulation, Modeling, and Programming for Autonomous Robots (SIMPAR 2018), 2018/05/16, Without Invitation, English
  7. A Compact Model for SiC Junction Barrier Schottky Diode for High-Voltage and High-Temperature Applications, F. Herrera, M. Miura-Mattausch, H.J. Mattausch, M. Takusagawa, J. Kobayashi, M. Hara, 2018 Workshop on Compact Modeling, 2018/05/13, With Invitation, English
  8. Modeling of Carrier Trapping and Its Impact on Switching Performance, Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Dondee Navarro, and Hans Jürgen Mattausch, Electron Devices Technology and Manufacturing (EDTM), 2018/03, With Invitation, English
  9. MOSFET optimization toward power efficient circuit design, 10. A. Mukhopadhyay, S. Bhattacharya, T. Iizuka, T. K. Maiti, M. Miura-Mattausch, A. Gau, D. Navarro, H. Rahaman, A. Sengupta and H. J. Mattausch, International Symposium on Devices, Circuits and Systems (ISDCS), 2018/03, Without Invitation, English
  10. Consistent Predictive Simulation of SRAM-Cell Performance Degradation Including Both MOSFET Fabrication Variation and Aging, Hiroaki Gau, Nezam Rohbani, Tapas K. Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, and Hirotaka Takatsuka, Electron Devices Technology and Manufacturing (EDTM), 2018/03, Without Invitation, English
  11. Compact Modeling of SiC Schottky Barrier Diode (SBD) and Its Extension to Junction Barrier Schottky Diode (JBS), Int. Conf. on Solid-State Devices and Materials (SSDM), 2017/09, Without Invitation, English
  12. Circuit-Aging Modeling Based on Dynamic MOSFET Degradation and Its Verification, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017/09, Without Invitation, English
  13. Compact Modeling of Normaly-on MOSFET Applicable for Any Technology Generations, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017/09, Without Invitation, English
  14. A Normally-on MOSFET Compact Model based on Surface Potential Description, Takahiro Iizuka, Takuya Umeda, Yoko Hirano, Hideyuki Kikuchihara, Mitiko Miura-Mattausch, and Hans Jürgen Mattausch, MOS-AK Workshop Program, 2017/09, With Invitation, English
  15. Aging Simulation of SiC-MOSFET in DC-AC Converter, Electron Devices Technology and Manufacturing (EDTM), 2017/02, Without Invitation, English
  16. Physics Based System Simulation for Robot Electro-Mechanical Control Design, Electron Devices Technology and Manufacturing (EDTM), 2017/02, Without Invitation, English
  17. Accurate Modeling of MOSFET Aging Based on Trap-Density Increase for Predicting Circuit Performance Aging, Electron Devices Technology and Manufacturing (EDTM), 2017/02, Without Invitation, English
  18. Analysis of 4H-SiC IGBT Switching in the Presence of Interface Traps using Miller Plateau Characteristics, Int. Conf. on Solid-State Devices and Materials (SSDM), 2016/09, Without Invitation, English
  19. Accurate IGBT Modeling under High-Injection Condition, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016/09, Without Invitation, English
  20. 4H-SiC IGBT Electrical Degradation Characteristics Due to Interface Defects, International Workshop on Compact Modeling, 2016/01, Without Invitation, English
  21. Investigation of 4H-SiC IGBT Turn-off Performance for Achieving Low Power Loss, International Conference on Solid State Devices and Materials (SSDM), 2015/09, Without Invitation, English
  22. Switching Characteristics of a 4H-SiC IGBT with Interface Defects Up to the Nonquasi-Static Regime, International Conference on Solid State Devices and Materials (SSDM), 2014/09, Without Invitation, English
  23. Degradation of 4H-SiC IGBT threshold characteristics due to SiC/SiO2 interface defects, International Semiconductor Device Research Symposium, 2013/12, Without Invitation, English
  24. Compact Modeling of the Punch-Through Effect in SiC-IGBT for 6.6kV Switching Operation with Improved Performance, European Conf. on Silicon Carbide & Related Materials (ECSCRM), 2012/09, Without Invitation, English
  25. Compact Modeling of Radiation Effects in Thin-Layer SOI-MOSFETs, M. Miura-Mattausch, H. Kikuchihara, S. Baba, D. Navarro, T. Iizuka, K Sakamoto, H. J. Mattausch, 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Without Invitation, English

Awards

  1. 2003, Presentation Award, Semiconductor Technology Academic Research Center (STARC)

Social Activities

Organizing Academic Conferences, etc.

  1. 2021 4th International Conference on Devices, Circuits and Systems
  2. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Technical Program Committee Member, 2017/
  3. IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Technical Program Committee Member, 2017/
  4. International Workshop on Compact Modeling, Technical Program Committee Member, 2016/01
  5. IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Co-Chair, Modeling Committee, 2018/, 2018/
  6. International Symposium on Devices, Circuits and Systems (ISDCS), Technical Program Committee Member, 2018/, 2019/
  7. IEEE Electron Devices Technology and Manufacturing Conference (EDTM) 2019, Chair, Modeling Committee, 2018/, 2019/

History as Peer Reviews of Academic Papers

  1. 2017, IEEE Trans on Electron Devices