TAKAHIRO IIZUKA

Last Updated :2025/03/03

Affiliations, Positions
Hiroshima University
E-mail
iizukahiroshima-u.ac.jp

Basic Information

Major Professional Backgrounds

  • 2012/04/01, Hiroshima University, HiSIM Research Center, Associate Professor
  • 2023/04, 9999, Hiroshima University, HiSIM Research Center

Academic Degrees

  • Doctor of Engineering, Hiroshima University
  • Master of Science, Kyoto University

Research Keywords

  • compact model
  • device physics
  • circuit simulation
  • device simulation
  • Process-Design Kit
  • carrier transport
  • semiconductor devices

Affiliated Academic Societies

  • IEEE, 1995, 9999

Research Activities

Academic Papers

  1. Analytical Vth Modeling for Dual-Gate MOSFETs With Independent Gate Control, IEEE Transactions on Electron Devices, 69(10), 5456-5461, 20221001
  2. Operating-Condition Optimization of MG-MOSFETs for Low-Voltage Application, 6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022, 97-99, 2022
  3. Optimization of Low-Voltage-Operating Conditions for MG-MOSFETs, IEEE Journal of the Electron Devices Society, 10, 913-919, 2022
  4. Miller-Capacitance Analysis of High-Voltage MOSFETs and Optimization Strategies for LowPower Dissipation, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2021-September, 44-47, 20210927
  5. History effect investigation in SOI MOSFET for minimizing impact on circuit performance, 4th International Symposium on Devices, Circuits and Systems, ISDCS 2021 - Conference Proceedings, 20210303
  6. Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit under High-Frequency Operation, IEEE Access, 9, 23786-23794, 2021
  7. Compact modeling of radiation effects in thin-layer SOI-MOSFETs, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2020-September, 319-322, 20200923
  8. Universal feature of trap-density increase in aged MOSFET and its compact modeling, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2020-September, 109-112, 20200923
  9. Predictive compact modeling of abnormal LDMOS characteristics due to overlap-length modification, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2020-September, 157-160, 20200923
  10. History Effect on Circuit Performance of SOI-MOSFETs, 3rd International Symposium on Devices, Circuits and Systems, ISDCS 2020 - Proceedings, 20200304
  11. Modeling of Short-Channel Effect on Multi-Gate MOSFETs for Circuit Simulation, 3rd International Symposium on Devices, Circuits and Systems, ISDCS 2020 - Proceedings, 20200304
  12. Carrier Dynamics in Lightly-doped Resistance Region in Power MOSFETs, 3rd International Symposium on Devices, Circuits and Systems, ISDCS 2020 - Proceedings, 20200304
  13. Compact Modeling of Multi-Gate MOSFETs for High-Power Applications, IEEE Journal of the Electron Devices Society, 8, 1381-1389, 2020
  14. Advanced Short-Channel-Effect Modeling With Applicability to Device Optimization - Potentials and Scaling, IEEE Transactions on Electron Devices, 66(9), 3726-3733, 201909
  15. Modeling of temperature-dependent mosfet aging, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2019-September, 201909
  16. Prevention of highly power-efficient circuits due to short-channel effects in MOSFETs, IEICE Transactions on Electronics, E102C(6), 487-494, 201906
  17. Validation on duality in impact-ionization carrier generation at the onset of snapback in power mosfets, 2019 2nd International Symposium on Devices, Circuits and Systems, ISDCS 2019 - Proceedings, 20190521
  18. Compact Modeling for Leading-Edge Thin-Layer MOSFETs with Additional Applicability in Device optimization toward Suppressed Short-Channel Effects, 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019, 29-31, 201903
  19. Potential-Based Modeling of Depletion-Mode MOSFET Applicable for Structural Variations, IEEE Transactions on Electron Devices, 66(1), 52-59, 201901
  20. Leading-Edge Thin-Layer MOSFET Potential Modeling Toward Short-Channel Effect Suppression and Device Optimization, IEEE Journal of the Electron Devices Society, 7, 1293-1301, 2019
  21. Recent Challenges in Compact Modeling of Short-Channel Effect for Leading-Edge Types of MOSFETs, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings, 20181205
  22. Consistent Modeling of Snapback Phenomenon Based on Conventional I-V Measurements, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2018-September, 159-162, 20181128
  23. Compact modeling for power efficient circuit design, European Solid-State Device Research Conference, 2018-September, 234-237, 20181008
  24. Compact modeling applicable for power efficient circuit design, 2018 International Symposium on Devices, Circuits and Systems, ISDCS 2018, 1-4, 20180611
  25. MOSFET optimization toward power efficient circuit design, 2018 International Symposium on Devices, Circuits and Systems, ISDCS 2018, 1-4, 20180611
  26. Compact modeling of normally-on mosfet applicable for any technology generations, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2017-September, 261-264, 20171025
  27. Compact modeling of power devices embedded in advanced low-power CMOS circuits, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 209-212, 20161020
  28. Modeling of NBTI stress induced hole-trapping and interface-state- generation mechanisms under a wide range of bias conditions, IEICE Transactions on Electronics, E96-C(10), 1339-1347, 201310
  29. Modeling of trench-gate type HV-MOSFETs for circuit simulation, IEICE Transactions on Electronics, E96-C(5), 744-751, 201305
  30. Analysis and modeling of geometry dependent thermal resistance in silicon-on-insulator metal-oxide-semiconductor field-effect transistors, Japanese Journal of Applied Physics, 52(4 PART 2), 201304
  31. Modeling of the impurity-gradient effect in high-voltage laterally diffused MOSFETs, IEEE Transactions on Electron Devices, 60(2), 684-690, 2013
  32. Parameter extraction and comparison of self-heating models for power MOSFETs based on transient current measurements, IEEE Transactions on Electron Devices, 60(2), 708-713, 2013
  33. The second-generation of HiSIM-HV compact models for high-voltage MOSFETs, IEEE Transactions on Electron Devices, 60(2), 653-661, 2013
  34. Compact reliability model for degradation of advanced p-MOSFETs due to NBTI and hot-carrier effects in the circuit simulation, IEEE International Reliability Physics Symposium Proceedings, 2013
  35. Compact modeling of expansion effects in LDMOS, IEICE Transactions on Electronics, E95-C(11), 1817-1823, 201211
  36. Self-heating parameter extraction of power metal-oxide-silicon field effect transistor based on transient drain current measurement, IETE Journal of Research, 58(3), 230-236, 201205
  37. Unified reaction-diffusion model for accurate prediction of negative bias temperature instability effect, Japanese Journal of Applied Physics, 51(2 PART 2), 201202
  38. Modeling of trench-gate type HV-MOSFETs for circuit simulation, Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012, 748-751, 2012
  39. Development of predictive model and circuit simulation methodology for negative bias temperature instability effects, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 213-216, 2012
  40. Characterization of time dependent carrier trapping in poly-crystalline tfts and its accurate modeling for circuit simulation, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 71-74, 2012
  41. Compact thermal-interaction model for dynamic within chip temperature determination by circuit simulation, IEEE International Conference on Microelectronic Test Structures, 187-190, 2012
  42. Experimental extraction of substrate-noise coupling between MOSFETs and its compact modeling for circuit simulation, IEEE International Conference on Microelectronic Test Structures, 101-104, 2012
  43. Self-heating parameter extraction of power MOSFETs based on transient drain current measurements and on the 2-cell self-heating model, IEEE International Conference on Microelectronic Test Structures, 191-195, 2012
  44. Accurate spice modeling of 80V power LDMOS with interdigitated source structure, Proceedings of the International Symposium on Power Semiconductor Devices and ICs, 101-104, 2012
  45. HiSIM-SOTB: A compact model for SOI-MOSFET with ultra-thin Si-layer and BOX, Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012, 792-795, 2012
  46. Modeling of DMOS device for high-voltage applications based on 2D current flow, Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012, 752-755, 2012
  47. Modeling of degradation caused by channel hot carrier and negative bias temperature instability effects in p-MOSFETs, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012
  48. Modeling of power devices for enabling smart energy consumption, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012
  49. Effect of carrier transit delay on complementary metal-oxide-semiconductor switching performance, Japanese Journal of Applied Physics, 49(4 PART 2), 201004
  50. An efficient method of calibrating MOSFET capacitances by way of excluding intra- DUT parasitic contributions, IEEE International Conference on Microelectronic Test Structures, 164-169, 2010
  51. Proposal of a fitting accuracy metric suitable for compact model qualification in all MOSFET operation regions, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 251-254, 2010
  52. Degraded frequency-tuning range and oscillation amplitude of LC-VCOs due to the Nonquasi-Static effect in MOS varactors, IEICE Transactions on Electronics, E92-C(6), 777-784, 2009
  53. Non-quasi-static carrier dynamics of MOSFETs under low-voltage operation, IEICE Transactions on Electronics, E92-C(5), 608-615, 2009
  54. Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations, Mathematics and Computers in Simulation, 79(4), 1096-1106, 20081215
  55. Frequency dependence of measured metal oxide semiconductor field-effect transistor distortion characteristic, Japanese Journal of Applied Physics, 47(4 PART 2), 2610-2615, 200804
  56. Non-quasi-static carrier dynamics of MOSFETs under low-voltage operation, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 1051-1054, 2008
  57. Surface-potential-based metal-oxide-silicon-varactor model for RF applications, Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 46(4 B), 2091-2095, 200704
  58. HiSIM2.4.0: Advanced MOSFET model for the 45nm technology node and beyond, 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings, 3, 479-484, 2007
  59. HiSIM-varactor: Complete surface-potential-based model for RF applications, 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings, 3, 621-624, 2007
  60. STARC'S semiconductor design technology research activities and the HISIM2 advanced mosfet model project, Proceedings of the 14th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2007, 41-46, 2007
  61. HiSIM2: Advanced MOSFET model valid for RF circuit simulation, IEEE Transactions on Electron Devices, 53(9), 1994-2006, 200609
  62. On the validity of conventional MOSFET nonlinearity characterization at RF switching, IEEE Microwave and Wireless Components Letters, 16(3), 125-127, 200603
  63. Noise modeling based on self-consistent surface-potential description for advanced MOSFETs aiming at RF applications, ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 1264-1267, 2006
  64. Analysis and compact modeling of MOSFET high-frequency noise, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 158-161, 2006
  65. Advanced compact MOSFET model HiSIM2 based on surface potentials with a minimum number of approximation, 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings, 3, 638-643, 2006
  66. Gate-length and drain-voltage dependence of thermal drain noise in advanced metal-oxide-semiconductor-field-effect transistors, Applied Physics Letters, 87(9), 20050829
  67. MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime, Proceedings of the Custom Integrated Circuits Conference, 2005, 827-830, 2005
  68. Noise modeling with HiSIM based on self-consistent surface-potential description, 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004, 2, 66-69, 2004
  69. MOSFET modeling for RF-circuit simulation, International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, 2, 1118-1122, 2004