Yasuaki Itou

Last Updated :2024/06/05

Affiliations, Positions
Graduate School of Advanced Science and Engineering, Professor
E-mail
yasuakihiroshima-u.ac.jp
Self-introduction
High-performance computing, Parallel computing, AI, Machine learning, Quantum computing, Quantum chemistry calculations, Embedded systems.

Basic Information

Academic Degrees

  • Doctor of Engineering, Hiroshima University
  • Master of Information Science, Japan Advanced Institute of Science and Technology\, Hokuriku

Research Fields

  • Informatics;Computing Technologies;Software

Research Keywords

  • Parallel processing
  • Reconfigurable computing
  • GPGPU
  • FPGA

Educational Activity

Course in Charge

  1. 2024, Liberal Arts Education Program1, Second Semester, Starting Programming from Scratch
  2. 2024, Liberal Arts Education Program1, 1Term, Introductory Seminar for First-Year Students
  3. 2024, Undergraduate Education, First Semester, Programming III
  4. 2024, Undergraduate Education, 3Term, Operating Systems
  5. 2024, Undergraduate Education, Intensive, Parallel and Distributed Processing
  6. 2024, Undergraduate Education, 3Term, Informatics and Data Science Exercise III(Before R3)
  7. 2024, Undergraduate Education, 4Term, Informatics and Data Science Exercise IV(Before R3)
  8. 2024, Undergraduate Education, 1Term, Informatics Seminar I
  9. 2024, Undergraduate Education, 2Term, Informatics Seminar II
  10. 2024, Undergraduate Education, Second Semester, Graduation Thesis
  11. 2024, Graduate Education (Master's Program) , 1Term, Special Exercises on Informatics and Data Science A
  12. 2024, Graduate Education (Master's Program) , 2Term, Special Exercises on Informatics and Data Science A
  13. 2024, Graduate Education (Master's Program) , 3Term, Special Exercises on Informatics and Data Science B
  14. 2024, Graduate Education (Master's Program) , 4Term, Special Exercises on Informatics and Data Science B
  15. 2024, Graduate Education (Master's Program) , 1Term, Special Exercises on Informatics and Data Science B
  16. 2024, Graduate Education (Master's Program) , 2Term, Special Exercises on Informatics and Data Science B
  17. 2024, Graduate Education (Master's Program) , Academic Year, Special Study on Informatics and Data Science
  18. 2024, Graduate Education (Master's Program) , 1Term, Embedded System
  19. 2024, Graduate Education (Doctoral Program) , Academic Year, Special Study on Informatics and Data Science

Research Activities

Academic Papers

  1. FM screening by the local exhaustive search, with hardware acceleration, INTERNATIONAL JOURNAL OF FOUNDATIONS OF COMPUTER SCIENCE, 16(1), 89-104, 200502
  2. An energy efficient leader election protocol for radio network with a single transceiver, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A(5), 1355-1361, 200612
  3. Efficient hardware algorithms for N choose K counters using the bitonic merger, INTERNATIONAL JOURNAL OF FOUNDATIONS OF COMPUTER SCIENCE, 18(3), 517-528, 200706
  4. A NEW FM SCREENING METHOD TO GENERATE CLUSTER-DOT BINARY IMAGES USING THE LOCAL EXHAUSTIVE SEARCH WITH FPGA ACCELERATION, INTERNATIONAL JOURNAL OF FOUNDATIONS OF COMPUTER SCIENCE, 19(6), 1373-1386, 200812
  5. LOW-LATENCY CONNECTED COMPONENT LABELING USING AN FPGA, INTERNATIONAL JOURNAL OF FOUNDATIONS OF COMPUTER SCIENCE, 21(3), 405-425, 201006
  6. AN EFFICIENT PARALLEL SORTING COMPATIBLE WITH THE STANDARD QSORT, INTERNATIONAL JOURNAL OF FOUNDATIONS OF COMPUTER SCIENCE, 22(5), 1057-1071, 201108
  7. A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E94D(12), 2378-2388, 201112
  8. A GPU Implementation of Dynamic Programming for the Optimal Polygon Triangulation, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E96D(12), 2596-2603, 201312
  9. Offline Permutation Algorithms on the Discrete Memory Machine with Performance Evaluation on the GPU, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E96D(12), 2617-2625, 201312
  10. A Classification Processor for a Support Vector Machine with embedded DSP slices and block RAMs in the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), 91-96, 201309
  11. A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, in Proc. of International Symposium on Computing and Networking (CANDAR), 75-84, 201312
  12. Accelerating computation of Euclidean distance map using the GPU with Efficient memory access, International Journal of Parallel, Emergent and Distributed Systems, 28(5), 383-406, 2013
  13. An Efficient Implementation of the Hough Transform using DSP slices and block RAMs on the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), 85-90, 201309
  14. An FPGA implementation for neural networks with the FDFM processor core approach, International Journal of Parallel, Emergent and Distributed Systems, 28(4), 308-320, 2013
  15. An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, in Proc. of 2013 International Conference on Parallel Processing (ICPP), 1-10, 20131001
  16. ASCII Art Generation using the Local Exhaustive Search on the GPU, in Proc. of International Symposium on Computing and Networking (CANDAR), 194-200, 201312
  17. Efficient Hough Transform on the FPGA using DSP slices and Block RAMs, in Proc. of Workshop on Advances in Parallel and Distributed Computational Models (APDCM), 771-778, 20130501
  18. Implementations of the Hough Transform on the Embedded Multicore Processors, International Journal of Networking and Computing (IJNC), 4(1), 174-188, 20140101
  19. Template Matching using DSP slices on the FPGA, in Proc. of International Symposium on Computing and Networking (CANDAR), 338-344, 201312
  20. The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), 79-84, 201309
  21. The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine, in Proc. of International Symposium on Computing and Networking (CANDAR), 95-103, 201312
  22. TinyCSE: Tiny Computer System for Education, in Proc. of International Symposium on Computing and Networking (CANDAR), 639-641, 201312
  23. Offline Permutation on the CUDA-enabled GPU, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E97D(12), 3052-3062, 201412
  24. An Optimal Implementation of the Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation on the GPU, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E97D(12), 3063-3071, 201412
  25. Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs, International Journal of Networking and Computing, 1(1), 49-62, 201101
  26. An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA, International Journal of Networking and Computing, 1(2), 277-289, 201107
  27. Accelerating the CKY parsing using FPGAs, IEICE Transactions on Information and Systems, E86-D(5), 803-810, 201312
  28. Instance-Specific Solutions to Accelerate the CKY Parsing for Large Context-free Grammars, International Journal on Foundations of Computer Science, 15(2), 403-416, 200404
  29. Implementations of a Parallel Algorithm for Computing Euclidean Distance Map in Multicore Processors and GPUs, International Journal of Networking and Computing, 1(2), 260-276, 201107
  30. The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption, International Journal of Networking and Computing, 2(1), 79-96, 201201
  31. An Algorithm to Obtain Circuits with Synchronous RAMs, Journal of Communication and Computer, 9(5), 547-559, 201212
  32. A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with Cycles, International Journal of Networking and Computing, 2(1), 269-290, 201207
  33. Accelerating ant colony optimisation for the travelling salesman problem on the GPU, International Journal of Parallel, Emergent and Distributed Systems, 29(4), 401-420, 20140801
  34. Bulk Execution of Oblivious Algorithms on the Unified Memory Machine, with GPU Implementation, Proc. of International Parallel and Distributed Processing Symposium Workshops, 586-595, 20140519
  35. An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA, Proc. of International Parallel and Distributed Processing Symposium Workshops, 762-770, 20140519
  36. C2CU : A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, Proc. of International Conference on Algorithms and Architectures for Parallel Processing, 178-191, 201408
  37. GPU-accelerated Verification of the Collatz Conjecture, Proc. of International Conference on Algorithms and Architectures for Parallel Processing, 483-496, 201408
  38. A GPU Implementation of Clipping-Free Halftoning using the Direct Binary Search, Proc. of International Conference on Algorithms and Architectures for Parallel Processing, 57-70, 201408
  39. Random Address Permute Shift Technique for the Shared Memory on GPUs, Proc. of International Conference on Parallel Processing Workshops, 429-483, 201409
  40. Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, Proc. of International Conference on Parallel Processing, 251-250, 201409
  41. Thorough Evaluation of GPU Shared Memory Load and Store Instructions, in Proc. of International Symposium on Computing and Networking, 614-616, 201412
  42. An Efficient Implementation of the One-Dimensional Hough Transform Algorithm for Circle Detection on the FPGA, in Proc. of International Symposium on Computing and Networking, 447-452, 201412
  43. Optimality of Fundamental Parallel Algorithms on the Hierarchical Memory Machine, with GPU implementation, Proc. of International Conference on Parallel, Distributed and Network-Based Processing, 626-634, 201503
  44. A character art generator using the local exhaustive search, with GPU acceleration, INTERNATIONAL JOURNAL OF PARALLEL EMERGENT AND DISTRIBUTED SYSTEMS, 31(1), 47-63, 201601
  45. Bulk execution of Euclidean algorithms on the CUDA-enabled GPU, International Journal of Networking and Computing, 6(1), 42-63, 201601
  46. Bulk GCD Computation Using a GPU to Break Weak RSA Keys, Proc. of International Parallel and Distributed Processing Symposium Workshops, 385-394, 201505
  47. GPU-accelerated Digital Halftoning by the Local Exhaustive Search, Proc. of the 14th International Symposium on Parallel and Distributed Computing, 82-87, 201506
  48. Optimal Parallel Hardware K-Sorter and TopK-Sorter, with FPGA implementations, Proc. of the 14th International Symposium on Parallel and Distributed Computing, 138-147, 201506
  49. Parallel FDFM Approach for Computing GCDs Using the FPGA, Proc. of 11th International Conference of Parallel Processing and Applied Mathematics, 238-247, 201509
  50. A Parallel Algorithm for LZW decompression, with GPU implementation, Proc. of 11th International Conference of Parallel Processing and Applied Mathematics, 228-237, 201509
  51. Fast LZW compression using a GPU, Proc. of International Symposium on Computing and Networking, 303-308, 201512
  52. A Warp-synchronous Implementation for Multiple-length Multiplication on the GPU, Proc. of International Symposium on Computing and Networking, 96-102, 201512
  53. A Fast Approximate String Matching Algorithm on GPU, Proc. International Symposium on Computing and Networking, 188-192, 201512
  54. Parallelization Techniques for Error Diffusion with GPU Implementations, Proc. of International Symposium on Computing and Networking, 30-39, 201512
  55. A flexible-length-arithmetic processor based on FDFM approach in FPGAs, Proc. of International Symposium on Computing and Networking, 364-370, 201512
  56. Efficient GPU implementations for the Conway's Game of Life, Proc. of International Symposium on Computing and Networking, 11-20, 201512
  57. Accelerating digital halftoning using the local exhaustive search on the GPU, Concurrency and Computation: Practice and Experience, Web(Web), Web-Web, 20160212
  58. An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E99D(12), 2901-2910, 201612
  59. Fully Parallelized LZW Decompression for CUDA-Enabled GPUs, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E99D(12), 2986-2994, 201612
  60. A Memory-Access-Efficient Implementation for Computing the Approximate String Matching Algorithm on GPUs, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E99D(12), 2995-3003, 201612
  61. GPU-Accelerated Bulk Execution of Multiple-Length Multiplication with Warp-Synchronous Programming Technique, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E99D(12), 3004-3012, 201612
  62. Fast Simulation of Conway's Game of Life Using Bitwise Parallel Bulk Computation on a GPU, INTERNATIONAL JOURNAL OF FOUNDATIONS OF COMPUTER SCIENCE, 27(8), 981-1003, 201612
  63. GPU-accelerated Exhaustive Verification of the Collatz Conjecture, International Journal of Networking and Computing, 7(1), 69-85, 201701
  64. Efficient Implementation of FDFM Approach for Euclidean Algorithms on the FPGA, International Journal of Networking and Computing, 6(2), 420-435, 201607
  65. Light Loss-Less Data Compression, with GPU implementation, Proc. of the 16th International Conference on Algorithms and Architectures for Parallel Processing, 281-294, 201612
  66. An Efficient Implementation of LZW Compression in the FPGA, Proc. of the 16th International Conference on Algorithms and Architectures for Parallel Processing, 512-520, 201612
  67. Accelerating Ant Colony Optimization for the Vertex Coloring Problem on the GPU, Proc. of International Symposium on Computing and Networking, 469-475, 201612
  68. A Memory-Access-Efficient Implementation of the Approximate String Matching Algorithm on GPU, Proc. of International Symposium on Computing and Networking, 483-489, 201612
  69. A hardware sorter for almost sorted sequences, with FPGA implementations, Proc. of International Symposium on Computing and Networking, 565-571, 201612
  70. An Evaluation of the Parallella Architecture for the Convex Hull Computation, Proc. of International Symposium on Computing and Networking, 704-706, 201612
  71. GPU-Accelerated Bulk Computation of the Eigenvalue Problem for Many Small Real Non-symmetric Matrices, Proc. of International Symposium on Computing and Networking, 490-496, 201612
  72. Bitwise Parallel Bulk Computation on the GPU, with Application to the CKY Parsing for Context-Free Grammars, Proc. of International Parallel and Distributed Processing Symposium Workshops, 589-598, 201605
  73. An Efficient Implementation of LZW Decompression in the FPGA, Proc. of International Parallel and Distributed Processing Symposium Workshops, 599-607, 201605
  74. C2CU: a CUDA C program generator for bulk execution of a sequential algorithm, CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 29(17), e4022, 20170910
  75. Adaptive loss-less data compression method optimized for GPU decompression, CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 29(24), e4283, 20171225
  76. An Efficient GPU Implementation of CKY Parsing Using the Bitwise Parallel Bulk Computation Technique, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E100D(12), 2857-2865, 201712
  77. Almost optimal column-wise prefix-sum computation on the GPU, JOURNAL OF SUPERCOMPUTING, 74(4), 1510-1521, 201804
  78. An Efficient GPU Implementation of Bulk Computation of the Eigenvalue Problem for Many Small Real Non-symmetric Matrices, International Journal of Networking and Computing, 7(2), 227-247, 201707
  79. Single Kernel Soft Synchronization Technique for Task Arrays on CUDA-enabled GPUs, Proc. of International Symposium on Computing and Networking, 11-20, 201711
  80. A Square Pointillism Image Generation, and its GPU Acceleration, Proc. of International Symposium on Computing and Networking, 38-47, 201711
  81. A Hybrid Architecture for the Approximate String Matching on an FPGA, Proc. of International Symposium on Computing and Networking, 48-57, 201711
  82. A GPU Implementation of Bulk Execution of the Dynamic Programming for the Optimal Polygon Triangulation, Proc. of 12th International Conference of Parallel Processing and Applied Mathematics, 314-323, 201709
  83. Almost Optimal Column-wise Prefix-sum Computation on the GPU, Proc. of 12th International Conference of Parallel Processing and Applied Mathematics, 224-233, 201709
  84. Simple and Fast Parallel Algorithms for the Voronoi Map and the Euclidean Distance Map, with GPU implementations, Proc. of 46th International Conference on Parallel Processing, 362-371, 201708
  85. Photomosaic Generation by Rearranging Subimages, with GPU Acceleration, Proc. of International Parallel and Distributed Processing Symposium Workshops, 942-951, 201705
  86. Accelerating the Smith-Waterman Algorithm Using Bitwise Parallel Bulk Computation Technique on GPU, Proc. of International Parallel and Distributed Processing Symposium Workshops, 932-941, 201705
  87. Efficient Byte Stream Pattern Test using Bloom Filter with Rolling Hash Functions on the FPGA, Proc. of International Symposium on Computing and Networking, 66-75, 201811
  88. A Prefix-Sum-Based Rabin-Karp Implementation for Multiple Pattern Matching on GPGPU, Proc. of International Symposium on Computing and Networking, 139-145, 201811
  89. Tile Art Image Generation Using Conditional Generative Adversarial Networks, Proc. of International Symposium on Computing and Networking Workshops, 209-215, 201811
  90. An Optimal Parallel Algorithm for Computing the Summed Area Table on the GPU, Proc. of International Parallel and Distributed Processing Symposium Workshops, 763-772, 201811
  91. Bulk execution of the dynamic programming for the optimal polygon triangulation problem on the GPU, CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 31(19), e4947, 20191010
  92. Accelerating the Smith-Waterman Algorithm Using the Bitwise Parallel Bulk Computation Technique on the GPU, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E102D(12), 2400-2408, 201912
  93. Efficient convolution pooling on the GPU, JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 138, 222-229, 20200401
  94. Folded Bloom Filter for High Bandwidth Memory, with GPU implementations, Proc. of International Symposium on Computing and Networking, 18-27, 201911
  95. Throughput-Optimal Hardware Implementation of LZW Decompression on the FPGA, Proc. of International Symposium on Computing and Networking Workshops, 78-83, 201911
  96. Efficient GPU Implementations to Compute the Diameter of a Graph, Proc. of International Symposium on Computing and Networking, 102-111, 201911
  97. Structured Sparse Fully-Connected Layers in the CNNs and its GPU Acceleration, Proc. of International Symposium on Computing and Networking Workshops, 148-154, 201911
  98. A Watercolor Painting Image Generation using Stroke-based Rendering, Proc. of International Symposium on Computing and Networking Workshops, 465-469, 201911
  99. Efficient cuDNN-compatible Convolution-Pooling on the GPU, Proc. of 13th International Conference of Parallel Processing and Applied Mathematics, 46-58, 201909
  100. Efficient Triangular Matrix Vector Multiplication on the GPU, Proc. of 13th International Conference of Parallel Processing and Applied Mathematics, 493-504, 201909
  101. Stained Glass Image Generation using Voronoi Diagram and its GPU Acceleration, Proc. of 13th International Conference of Parallel Processing and Applied Mathematics, 396-407, 201909
  102. FIFO-Based Hardware Sorters for High Bandwidth Memory, Proc. of International Parallel and Distributed Processing Symposium Workshops, 663-672, 201905
  103. A Rabin-Karp Implementation for Handling Multiple Pattern-Matching on the GPU, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E103D(12), 2412-2420, 202012
  104. Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA, CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 33(12), e5623, 20210625
  105. Tile art image generation using parallel greedy algorithm on the GPU and its approximation with machine learning, CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 33(12), e5623, 20210625
  106. Efficient GPU Implementation for Solving the Maximum Independent Set Problem, Proc. of International Symposium on Computing and Networking, 29-38, 202011
  107. Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA, Proc. of International Symposium on Computing and Networking, 39-48, 202011
  108. Art Font Image Generation with Conditional Generative Adversarial Networks, Proc. of International Symposium on Computing and Networking Workshops, 151-156, 202011
  109. Huffman Coding with Gap Arrays for GPU Acceleration, Proc. of International Conference on Parallel Processing, article no. 1, 202008
  110. Adaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs, Proc. of International Conference on Parallel Processing, article no. 62, 202008
  111. An Efficient Multicore CPU Implementation for Convolution-Pooling Computation in CNNs, Proc. of International Parallel and Distributed Processing Symposium Workshops, 548-556, 202005
  112. A Work-Time Optimal Parallel Exhaustive Search Algorithm for the QUBO and the Ising model, with GPU implementation, Proc. of International Parallel and Distributed Processing Symposium Workshops, 557-566, 202005

Invited Lecture, Oral Presentation, Poster Presentation

  1. Fully Parallelized Lossless LZW decompression for CUDA-enabled GPUs, Koji Nakano, Koji Nakano, Shunji Funasaka, Yasuaki Ito, GPU Technology Conference (GTC 2016), 2016/05, Without Invitation, English, San Jose, USA
  2. Bitwise Parallel Bulk Computation for CKY Parsing, with the GPU implementation, Toru Fujita, Toru Fujita, Koji Nakano, Yasuaki Ito, GPU Technology Conference (GTC Japan 2016), 2016/10, Without Invitation, English, Tokyo
  3. Efficient Loss-Less Data Compression, with GPU implementation, Shunji Funasaka, Shunji Funasaka, Koji Nakano and Yasuaki, GPU Technology Conference (GTC Japan 2016), 2016/10, Without Invitation, English, Tokyo
  4. Bulk Computation of Eigenvalues of Many Small Real Non-symmetric Matrices on the GPU, Takumi Honda, Hiroki Tokura, Takumi Honda, Yasuaki Ito, Koji Nakano, Mitsuya Nishino, Yushiro Hirota, Masami Saeki, GPU Technology Conference (GTC Japan 2016), 2016/10, Without Invitation, English, Tokyo
  5. A Very Fast Data Compression Method Optimized for GPU Decompression, Koji Nakano, Koji Nakano, Shunji Funasaka, Yasuaki Ito, The GPU Technology Conference (GTC 2017), 2017/05, Without Invitation, English, San Jose, USA
  6. A Photomosaic Method by Rearranging Divided Images with GPU Acceleration, Yasuaki Ito, Yi Yang, Yasuaki Ito, Koji Nakano, Jacir L. Bordim, The GPU Technology Conference (GTC 2017), 2017/05, Without Invitation, English
  7. GPU Applications with Single Kernel Synchronization Technique, Shunji Funasaka, Shunji Funasaka, Koji Nakano, Yasuaki Ito, GPU Technology Conference (GTC Japan 2017), 2017/12, Without Invitation, English, Tokyo
  8. GPU Implementation of Image Generation for Square Pointillism, Hiroki Tokura, Hiroki Tokura, Yasuaki Ito, Koji Nakano, GPU Technology Conference (GTC Japan 2017), 2017/12, Without Invitation, English, Tokyo
  9. Parallel High-Quality Art Generation From Any Image Using A GPU, Hiroki Tokura, Yuki Kuroda, Yasuaki Ito, and Koji Nakano, Hiroki Tokura, Yuki Kuroda, Yasuaki Ito, and Koji Nakano, The GPU Technology Conference, 2018/05, Without Invitation, English, San Jose, USA

Awards

  1. 2020/08/20, Best Paper Award, ICPP Organizing Committee, Huffman Coding with Gap Arrays for GPU Acceleration
  2. 2020/11/27, Best Paper Award, Organizing Committee, Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA
  3. 2020/11/27, Best Paper Award, GCA Organizing Committee, Art Font Image Generation with Conditional Generative Adversarial Networks
  4. 2019/11/28, The 4th International Workshop on GPU Computing and AI Best Paper Award, GCA Organizing Committee, Structured Sparse Fully-Connected Layers in the CNNs and its GPU Acceleration
  5. 2018/11/29, The 6th International Symposium on Computing and Networking Best Paper Award, CANDAR Organizing Committee
  6. 2017/11/20, The 5th International Symposium on Computing and Networking Outstanding Paper Award, CANDAR 2017 Organizing Committee
  7. 2016/11/23, Best Paper Award The 8th International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), PDAA Organizing Committee
  8. 2016/12/15, Best Student Paper Award 16th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), ICA3PP General Chair
  9. 2015/12/10, Outstanding Paper Award, CANDAR Organizing Committee
  10. 2015/12/10, Best Paper Award, CANDAR Organizing Committee

External Funds

Acceptance Results of Competitive Funds

  1. KAKENHI(Grant-in-Aid for Scientific Research (C)), 2020, 2022
  2. 2019/04/01, 2020/03/31
  3. KAKENHI, 2016, 2018
  4. KAKENHI, 2013, 2015
  5. KAKENHI, 2012, 2015
  6. KAKENHI, Research on abstract modelsof FPGAs and evaluation of hardware algorithms, 2009, 2012
  7. KAKENHI, A study on establishment of a theory for accelerating computation based on partial-computation using FPGAs, 2008, 2011
  8. KAKENHI, 2005, 2007
  9. KAKENHI, 2005, 2008

Social Activities

History as Committee Members

  1. Finance & Publication Chair, 2022/01, 2022/12, International Symposium on Computing and Networking (CANDAR)
  2. Guest Editor, 2021/12, 2021/11, Concurrency and Computation Practice and Experience (CCPE) special issue on CANDAR 2021
  3. Guest Editor, 2021/12, 2022/11, International Journal of Networking and Computing (IJNC) special issue on CANDAR 2021
  4. Guest Associate Editor, 2021/10, 2022/11, Special Section on Forefront Computing of IEICE Transactions on Information and Systems
  5. Guest Editor, 2021/02, 2021/07, International Journal of Networking and Computing (IJNC) special issue on CANDAR 2020
  6. Guest Editor, 2021/01, 2021/01, Concurrency and Computation Practice and Experience (CCPE) special issue on CANDAR 2020
  7. Guest Associate Editor, 2019/12, 2021/12, Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking of IEICE Transactions on Information and Systems
  8. Guest Editor, 2019/12, 2020/12, Concurrence and Computation Practice and Experience (CCPE) special issue on CANDAR 2019
  9. Workshop Co-chair, 2019/04, 2022/11, International Workshop on GPU Computing and AI
  10. Guest Editor, 2019/01, 2019/10, Concurrence and Computation Practice and Experience (CCPE) special issue on CANDAR 2018
  11. Program Committee, 2019/01, 2019/05, The 9th International Workshop on Networking, Computing, Systems, and Software
  12. Program Committee, 2018/04, 2018/12, International Conference on Algorithms and Architectures for Parallel Processing
  13. Guest Editor, 2018/02, 2018/07, International Journal of Networking and Computing
  14. Program Committee, 2018/01, 2018/09, International Conference on Algorithms and Architectures for Parallel Processing
  15. Program Committee, 2017/11, 2018/05, Workshop on Advances in Parallel and Distributed Computational Models
  16. Guest Associate Editor, 2017/06, 2020/12, Special Section on Parallel and Distributed Computing and Networking of IEICE Transactions on Information and Systems
  17. Editor, 2017/05, 9999/99/99, International Journal of Networking and Computing
  18. Program Committee, 2017/03, 2018/12, International Workshop on Parallel and Distributed Algorithms and Applications
  19. Guest Editor, 2017/02, 2017/07, International Journal of Networking and Computing
  20. Workshop Co-chair, 2017/01, 2019/12, International Workshop on GPU Computing and Applications
  21. Program Committee, 2017/01, 2017/08, International Conference on Algorithms and Architectures for Parallel Processing
  22. Workshop Co-chair, 2016/04, 2017/12, International Workshop on GPU Computing and Applications
  23. Special Section on Parallel and Distributed Computing and Networking of IEICE Transactions on Information and Systems, Guest Associate Editor, 2015/12, 2017/12, IEICE
  24. Guest Editor, 2014/02, 2014/04, International Journal of Networking and Computing
  25. Registration and Finance Chair, 2013/03, 2021/12, International Symposium on Computing and Networking
  26. Program Committee, 2012/04, 2022/12, International Workshop on Parallel and Distributed Algorithms and Applications
  27. Secretariat, 2010/12, 9999/99, International Journal of Networking and Computing
  28. Program Committee, 2008/12, 2022/05, Workshop on Advances in Parallel and Distributed Computational Models

Organizing Academic Conferences, etc.

  1. The Sixth International Workshop on GPU Computing and Applications, Workshop co-chair, 2021/01, 2021/12
  2. The Fourth International Workshop on GPU Computing and Applications, Workshop Co-chair, 2019/01, 2019/12
  3. The Second International Workshop on GPU Computing and Applications, Workshop Co-chair, 2017/01, 2017/12
  4. The First International Workshop on GPU Computing and Applications, Workshop Co-chair, 2016/01, 2016/12
  5. The third International Workshop on GPU Computing and AI, Workshop co-chair, 2018/01, 2018/12
  6. The Fifth International Workshop on GPU Computing and Applications, Workshop Co-chair, 2020/01, 2020/12