Anri Nakajima

Last Updated :2025/01/07

Affiliations, Positions
Research Institute for Nanodevices, Associate Professor
E-mail
anakajimahiroshima-u.ac.jp

Basic Information

Academic Degrees

  • Doctor of Science, TOHOKU UNIVERSITY
  • Master of Science, TOHOKU UNIVERSITY

Research Fields

  • Interdisciplinary science and engineering;Applied physics;Applied materials

Research Keywords

  • single electron devices
  • gate dielectrics
  • atomic-layer deposition

Educational Activity

Course in Charge

  1. 2024, Undergraduate Education, 3Term, Semiconductor Process Engineering
  2. 2024, Undergraduate Education, Year, Graduation Thesis
  3. 2024, Graduate Education (Master's Program) , First Semester, Seminar on Electronics A
  4. 2024, Graduate Education (Master's Program) , Second Semester, Seminar on Electronics B
  5. 2024, Graduate Education (Master's Program) , Academic Year, Academic Presentation in Electronics
  6. 2024, Graduate Education (Master's Program) , 1Term, Exercises in Electronics A
  7. 2024, Graduate Education (Master's Program) , 2Term, Exercises in Electronics A
  8. 2024, Graduate Education (Master's Program) , 3Term, Exercises in Electronics B
  9. 2024, Graduate Education (Master's Program) , 4Term, Exercises in Electronics B
  10. 2024, Graduate Education (Master's Program) , 2Term, Molecular and Bio Devices Engineering
  11. 2024, Graduate Education (Master's Program) , Academic Year, Advanced Study in Quantum Matter
  12. 2024, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Quantum Matter

Research Activities

Academic Papers

  1. Growth and electrical properties of atomic-layer deposited ZrO2/Si-nitride stack gate dielectrics, JOURNAL OF APPLIED PHYSICS, 95(2), 536-542, 20040115
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  2. Application of highly-doped Si single-electron transistors to an exclusive-NOR operation, JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS, 43(3B), L418-L420, 20040315
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  3. Interface trap generation induced by charge pumping current under dynamic oxide field stresses, IEEE ELECTRON DEVICE LETTERS, 26(3), 216-218, 200503
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  4. Abnormal enhancement of interface trap generation under dynamic oxide field stress at MHz region, APPLIED PHYSICS LETTERS, 86(8), 20050221
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  5. Modified direct-current current-voltage method for interface trap density extraction in metal-oxide-semiconductor field-effect-transistor with tunneling gate dielectrics at high temperature, JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 44(1-7), L60-L62, 2005
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  6. Room-temperature operation of an exclusive-OR circuit using a highly doped Si single-electron transistor, APPLIED PHYSICS LETTERS, 86(12), 20050321
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  7. Enhancement of BTI degradation in pMOSFETs under high-frequency bipolar gate bias, IEEE ELECTRON DEVICE LETTERS, 26(6), 387-389, 200506
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  8. Atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics for future high-speed DRAM with enhanced reliability, IEEE ELECTRON DEVICE LETTERS, 26(8), 538-540, 200508
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  9. Annealing temperature dependence on nickel-germanium solid-state reaction, JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 44(24-27), L753-L755, 2005
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  10. Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics, JOURNAL OF APPLIED PHYSICS, 98(11), 20051201
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  11. Periodic Coulomb oscillations in Si single-electron transistor based on multiple islands, JOURNAL OF APPLIED PHYSICS, 98(12), 20051215
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  12. Influence of bulk bias on negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin SiON gate dielectrics, JOURNAL OF APPLIED PHYSICS, 99(6), 20060315
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  13. Carrier mobility in metal-oxide-semiconductor field effect transistor with atomic-layer-deposited Si-nitride gate dielectrics, JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 44(28-32), L903-L905, 2005
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  14. Pulse waveform dependence on AC bias temperature instability in pMOSFETs, IEEE ELECTRON DEVICE LETTERS, 26(9), 658-660, 200509
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  15. Mechanism of dynamic bias temperature instability in p- and nMOSFETs: The effect of pulse waveform, IEEE TRANSACTIONS ON ELECTRON DEVICES, 53(8), 1805-1814, 200608
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  16. Electron detrapping characteristics in positive bias temperature stressed n-channel metal-oxide-semiconductor field-effect transistors with ultrathin HfSiON gate dielectrics, APPLIED PHYSICS LETTERS, 91(3), 20070716
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  17. Atomic layer deposition of HfO2 using Hf[N(C2H5)(2)](4) and H2O, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 45(9A), 7091-7093, 200609
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  18. Cotunneling current in Si single-electron transistor based on multiple islands, APPLIED PHYSICS LETTERS, 89(18), 20061030
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  19. Improvement in mobility and negative-bias temperature instability in metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Si-nitride/SiO2 stack dielectrics, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(4B), 1874-1878, 200704
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  20. Ar annealing for suppression of gate oxide thinning at shallow trench isolation edge, IEEE ELECTRON DEVICE LETTERS, 28(7), 562-564, 200707
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  21. Electrical characteristics of Si single-electron transistor based on multiple islands, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(9B), 6233-6236, 200709
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  22. Atomic layer deposition of HfO2 and Si nitride on Ge substrates, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(12), 7699-7701, 200712
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  23. Bias temperature instability in metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Si-nitride/SiO(2) stack gate dielectrics, JOURNAL OF APPLIED PHYSICS, 103(8), 20080415
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  24. Silicon single-electron memory having in-plane dot with double gates, JAPANESE JOURNAL OF APPLIED PHYSICS, 47(6), 4985-4987, 200806
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  25. Dependence of charge storage and programming characteristics on dot number of floating dot memory, APPLIED PHYSICS LETTERS, 92(22), 20080602
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  26. ★, Impact of floating dot distribution on memory characteristics of self-aligned dots-on-nanowire memory, JOURNAL OF APPLIED PHYSICS, 105(11), 20090601
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  27. Conduction Path Fluctuation in Silicon Two-Dimensional Tunnel Junction Array, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(6), 200906
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  28. Fabrication of Si Nanowire Field-Effect Transistor for Highly Sensitive, Label-Free Biosensing, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(6), 200906
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  29. Monte Carlo Simulation of the Two-Dimensional Site Percolation Problem for Designing Sensitive and Quantitatively Analyzable Field-Effect Transistors, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(10), 200910
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  30. Effect of an Ultrathin SiN Cap Layer on the Bias Temperature Instability in Metal-Oxide-Semiconductor Field-Effect Transistors with HfSiON Gate Stacks, JAPANESE JOURNAL OF APPLIED PHYSICS, 49(12), 2010
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  31. Functional gate metal-oxide-semiconductor field-effect transistors using tunnel injection/ejection of trap charges enabling self-adjustable threshold voltage for ultralow power operation, APPLIED PHYSICS LETTERS, 98(5), 20110131
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  32. Highly sensitive ion detection using Si single-electron transistors, APPLIED PHYSICS LETTERS, 98(12), 20110321
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  33. Influence of Organic Contaminantion on Reliability and Trap Generation in MOS Devices, Extend. Abst. of Int. Conf. on Solid State Devices and Materials, 176-177, 20010401
  34. Fabrication Technologies for Double-SiO2-Barrier MOS Transistor with a Poly-Si Dot, Jpn. J. Appl. Phys., 40(3B), 2017-2020, 20010301
  35. Low-Temperature Selective Deposition of Silicon by Time-Modulation Exposure of Disilane and Formation of Silicon Nanowires, Extend. Abst. of Int. Conf. on Solid State Devices and Materials, 202-203, 20000401
  36. Self-Limiting Atomic-Layer Selective Deposition of Silicon Nitride by Temperature-Controlled Method, Extend. Abst. of Int. Conf. on Solid State Devices and Materials, 22-23, 19980401
  37. ★, Si quantum dot formation with low-pressure chemical vapor deposition, Jpn. J. Appl. Phys., 35(part2, 2B), L189-L191, 19960201
  38. Isolated nanometer-size Si dot arrays fabricated using electron-beam lithography, reactive ion etching, and Wet Etching in NH4OH/H2O2/H2O, Jpn. J. Appl. Phys., 33(part2, 12B), L1796-L1798, 19941201
  39. ★, Defect-induced Raman spectra in doped CeO2, Phys. Rev. B, 50(18), 13297-13307, 19941101
  40. Local-hopping mechanism of the O2- vacancy in stabilized ZrO2 studied by measuring the integrated intensity of quasielastic light scattering, Phys. Rev. B, 49(21), 14949-14957, 19940601
  41. Interpretation of the temperature dependence of the luminescence intensity, lifetime, and decay profiles in porous Si, Phys. Rev. B, 49(16), 11005-11009, 19940401
  42. Luminescence spectroscopy of porous Si by selective excitation, J. Phys. Soc. Jpn., 63(suppl. B), 190-202, 19940401
  43. c-Si like phonon structures in the luminescence of porous Si, J. Luminescence, 60＆61, 324-326, 19940401
  44. ★, Observation of phonon structures in porous Si luminescence, Phys. Rev. Lett., 70(23), 3659-3662, 19930601
  45. Microstructure of porous silicon, Appl. Phys. Lett., 62(21), 2631-2633, 19930501
  46. c-Si-like phonon structures in the luminescence of porous Si:, 9th International Conference on Luminescence and Optical Spectroscopy of Condensed Matter, M5-21, 19930401
  47. Quantum-size effect from photoluminescence of low-temperature-oxidized porous Si, Jpn. J. Appl. Phys., 32(part1, 1B), 415-418, 19930101
  48. ★, Photoluminescence of porous Si, oxidized then deoxidized chemically, Appl. Phys. Lett=, 61(1), 46-48, 19920701
  49. The evidence of quantum size effect from photoluminescence of low temperature oxdized porous Si, 1994 International Conf. on Solid State Devices and Materials, 472-474, 19920801
  50. Local structures in the superionic conductor Y3+-doped CeO2 studied using site-selective spectroscopy, Phys. Rev. B, 44(10), 4862-4871, 19910401
  51. Soft-breakdown-suppressed ultrathin atomic-layer-deposited silicon nitride/SiO2 stack gate dielectrics for advanced complementary metal-oxide-semiconductor technology, Appl. Phys. Lett=, 79(21), 3488-3490, 20011101
  52. Characterization of atomic-layer-deposited silicon nitride/SiO2 staked gate dielectrics for highly reliable p-metal-oxide-semiconductor field-effect transistors, B 19(4), 1138-1143, 20010701
  53. Low-temperature formation of silicon nitride gate dielectrics by atomic-Layer depositon:, Appl. Phys. Lett=, 79(5), 665-667, 20010701
  54. Self-limiting atomic-layer deposition of Si on SiO2 by alternate supply of Si2H6 and SiCl4:, Appl. Phys. Lett=, 79(5), 617-619, 20010701
  55. Low-temperature selective deposition of silicon on silicon nitride by time-modulated disilane flow and formation of silicon narrow wires, Appl. Phys. Lett=, 79(4), 494-496, 20010701
  56. Conduction mechanism in extremely thin poly-Si wires---width dependence of Coulomb blockade effect---, Extend. Abst.2001 Int. Conf. on Solid State Devices and Materials, 438-439, 20010901
  57. Atomic-layer-deposited silicon nitride/SiO2 stacked gate dielectrics for highly reliable p-MOSFETs, Applied Physics Letters, 77(18), 2855-2857, 20000101
  58. Fabrication of novel double-barrier MOS transistors with poly-Si dots, Abst. of Intern. Symp. on Formation= Physics and Device Application of Quantum Dot Structures, 10-10, 20000401
  59. Characterization of silicon/oxide/nitride layers by X-ray photoelectron spectroscopy, Applied Physics Letters, 75(11), 1535-1537, 19990901
  60. Si single-electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-alighed process, B17(5), 2163-2172, 19990401
  61. Microstructure and electrical properties of Sb nanocrystals formed in thin, thermally grown SiO2 layers by low-energy ion implantation, B 17(4), 1317-1322, 19990401
  62. Calculation of electrical properties of novel double-barrier metal oxide semiconductor transistors, Jpn. J. Appl. Phys., 38(part1,1B), 399-402, 19990101
  63. Silicon single-electron memory using ultra-small floating gate, 34(2), 142-152, 19980401
  64. Coulomb blockade in Sb nanocrystals formed in thin, thermally grown SiO2 layers by low-energy ion implantation, Appl. Phys. Lett=, 73(8), 1071-1073, 19980401
  65. ★, Microstructure and electrical properties of Sn nanocrystals in thin, thermally grown SiO2 layers formed via low energy ion implantation, J. Appl. Phys., 84(3), 1316-1320, 19980401
  66. Theoretical analysis of write errors and number of stored electrons for ten-nanoscale Si floating-dot memory, Jpn. J. Appl. Phys., 37(part2, 6B), L709-L711, 19980601
  67. Calculation of electrical properties of novel double-barrier MOS transistors, Abst. of Intern. Symp. on Formation= Physics and Device Application of Quantum Dot Structures, 10-10, 19980401
  68. Observation of periodic current oscillations in vertical sub-100 nm MOS-PDBFETs with wide channels, 1999 Silicon Nanoelectronics Workshop (Kyoto= June 12-13= 1999), 27-28, 19980601
  69. Coulomb blockade in Sb nanocrystals in thin SiO2 film formed by using low-energy ion implantation, Silicon Nanoelectronics Workshop 1998, 11-12, 19980601
  70. Single Electron Charging Effect of Sn Nanocrystals in Thin SiO2 Film Formed by Low Energy Ion Implantation, J81-C-II(2), 274-275, 19980401
  71. Formation of Sn nanocrystals in SiO2 film using low-energy ion implantation, Appl. Phys. Lett=, 71(25), 3652-3654, 19971201
  72. Formation of Sb nanocrystals in SiO2 film using ion implantation followed by thermal annealing, Jpn. J. Appl. Phys., 36(part2,11B), L1552-L1554, 19971101
  73. ★, Si single electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-aligned process, Appl. Phys. Lett=, 71(3), 353-355, 19970701
  74. Single electron charging of Sn nanocrystals in thin SiO2 film formed by low energy ion implantation, Technical Digest of the 1997 IEEE International Electron Devices Meeting, 159-162, 19971201
  75. Si single electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-aligned process, 1999 Silicon Nanoelectronics Workshop (Kyoto= June 12-13= 1999), 26-27, 19970601
  76. ★, Room temperature operation of Si single-electron memory with self-aligned floating dot gate, Appl. Phys. Lett=, 70(13), 1742-1744, 19970301
  77. ★, Microstructure and optical absorption properties of Si nanocrystals fabricated with low-pressure chemical-vapor deposition, J. Appl. Phys., 80(7), 4006-4011, 19961001
  78. Room temperature operation of Si single-electron memory with self-aligned floating dot gate, Technical Digest of the 1997 IEEE International Electron Devices Meeting, 952-954, 19961201
  79. Site-selective spectroscopy of Eu3+ in YSZ and Y3+-doped CeO2, Solid State Ionics, 40/41, 316-319, 19900401
  80. Investigations of valence charge of Tb ions in ZrO2-Tb4O7 mixed conductor using XANES measurements, Solid State Ionics, 35, 323-327, 19890401
  81. Site-selective spectroscopy of Eu3+ in YSZ and Y3+-doped CeO2, 7th Internantional Conference on Solid State Ionics=, 258, 19891101
  82. Determination of ionic diffusion coefficients and activation energies in (ZrO2)1-x(YbO1.5)x system by using quasielastic light scattering, Solid State Ionics, 28-30, 512-517, 19880401
  83. Raman and hyper-Raman scattering in oxide ion conductors, 6th International Conference Solid State Ionics, 147, 19870901
  84. Influence of Wafer Storage Environment on MOS Device Characteristics, 17(2), 96-104, 20020601
  85. Local-hopping mechanism of an oxygen vacancy in ZrO2 doped with Sc3+ studied by measuring quasi-elastic light scattering, Solid State Ionics, 146, 133-141, 20020101
  86. NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability, Appl. Phys. Lett=, 80(7), 1252-1254, 20020201
  87. Low thermal-budget ultrathin NH3-annealed atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics with excellent reliability, IEEE Electron Device Lett., 23(4), 179-181, 20020401
  88. Coulomb blockade effects and conduction mechanism in extremely thin polycrystalline-silicon wires, J. Appl. Phys., 91(8), 5213-5220, 20020401
  89. Reliable extraction of the energy distribution of Si/SiO2 interface traps in ultrathin metal-oxide-semiconductor structures, Appl. Phys. Lett=, 80(21), 3952-3954, 20020501
  90. Fabrication of Si single-electron transistors having double SiO2 barriers, Appl. Phys. Lett=, 80(24), 4617-4619, 20020601
  91. Conduction mechanism of Si single-electron transistors having an one-dimensional regular array of multiple tunnel junctions, Appl. Phys. Lett=, 81(4), 733-735, 20020701
  92. High quality NH3-annealed atomic Layer Deposited Si-nitride/SiO2 Stack Gate Dielectrics for Sub-100nm Technology Generations, Solid State Electron, 46, 1657-1662, 20020401
  93. Low-temperature formation of highly-reliable silicon-nitride gate dielectrics with suppressed soft-breakdown phenomena for advanced complementary metal-oxide-semiconductor technology, 20(4), 1406-1409, 20020701
  94. Atomic-layer deposition of ZrO2 with a Si nitiride barrier layer, Appl. Phys. Lett=, 81(15), 2824-2826, 20021001
  95. Response to "Comment on ’Reliable extraction of the energy distribution of Si/SiO2 interface traps in ultrathin metal-oxide-semiconductor structures’" [Appl. Phys. Lett. 81, 3681(2002)], Appl. Phys. Lett=, 81(19), 3683-3684, 20021101
  96. ★, Atomic-layer-deposited silicon-nitride/SiO2 stack ---- a highly potential gate dielectrics for advanced CMOS technology, Microelectronics Reliability, 42, 1823-1835, 20021201
  97. Soft breakdown free atomic-layer-deposited silicon-nitride/SiO2 stack gate dielectrics, Technical Digest of the 2001 IEEE International Electron Devices Meeting, 133-136, 20011201
  98. Ultrathin NH3 annealed atomic layer deposited Si-nitride/SiO2 stack gate dielectrics with high reliability, 2001 International Semiconductor Device Research Symposium, 26-29, 20011201
  99. Atomic-layer-deposition of Si nitride and ZrO2 for gate dielectrics, Abst. AVS Topical Conference on Atomic Layer Deposition (ALD 2002), 6-6, 20020801
  100. A novel method for extracting the energy distribution of Si/SiO2 interface traps in ultrathin oxide MOS structures, the Second IEEE Conference on Nanotechnology, 20020801
  101. Time-dependent breakdown of ultrathin SiO2 gate dielectrics under static and dynamic stress, Abst. 2nd ECS Int. Semiconductor Technology Conf., Abstract No.71, 20020901
  102. A comparative study of bulk and interface trap generation in ultrathin SiO2 and atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics, Forth Int. Symposium on Control of Semiconductor Interface (ISCSI-IV), A6-3-A6-3, 20021001
  103. An Effective Method for Obtaining Interface Trap Distribution in MOS capacitors with Tunneling Gate Oxides, Proceedings 2002 IEEE Int. Conf. on Semiconductor Electronics (ICSE 2002), 402-406, 20021201
  104. Organic Contamination Dependence of Process Induced Interface Trap Generation in Ultrathin Oxide Metal　Oxide　Semiconductor Transistors, Jpn. J. Appl. Phys., 42(12A), L1429-L1432, 20031201
  105. High quality atomic-layer-deposited ultrathin Si-nitride gate dielectrics with low density of interface and bulk traps, APPLIED PHYSICS LETTERS, 83(2), 335-337, 20030714
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  106. Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics, IEEE ELECTRON DEVICE LETTERS, 24(7), 472-474, 200307
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  107. Biomolecule detection based on Si single-electron transistors for highly sensitive integrated sensors on a single chip, APPLIED PHYSICS LETTERS, 100(2), 20120109
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  108. In-Plane Grain Orientation Alignment of Polycrystalline Silicon Films by Normal and Oblique-Angle Ion Implantations, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 201204
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  109. Charge redistribution in a charge storage layer containing C-60 molecules and organic polymers for long electron retention, APPLIED PHYSICS LETTERS, 101(21), 20121119
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  110. Characteristics of metal-oxide-semiconductor field-effect transistors with a functional gate using trap charging for ultralow power operation, JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 31(1), 201301
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  111. Excellent retention characteristics of nanocomposite gate insulator consisting of fullerene-containing polystyrene, APPLIED PHYSICS LETTERS, 103(1), 20130701
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  112. ★, Biomolecule detection based on Si single-electron transistors for practical use, APPLIED PHYSICS LETTERS, 103(4), 20130722
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  113. ★, Memory operation mechanism of fullerene-containing polymer memory, APPLIED PHYSICS LETTERS, 106(10), 103302-1-103302-5, 20150309
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  114. Dependence of memory characteristics of fullerene-containing polymer on the kind of gate metal, JAPANESE JOURNAL OF APPLIED PHYSICS, 54(10), 201510
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  115. Novel polymer composite having diamond particles and boron nitride platelets for thermal management of electric vehicle motors, JAPANESE JOURNAL OF APPLIED PHYSICS, 55(2), 027101-1-027101-8, 201602
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  116. ★, Application of Single-Electron Transistor to Biomolecule and Ion Sensors, Appllied Sciences, 6(4), 94-1-94-4, 20160401
  117. ★, Mechanism of Static and Dynamic Bias Temperature Instability in p- and n-MOSFETs, ECS transaction, 6(3), 203-228, 2007
  118. ★, Fullerene-Containing Electrically Conducting Electron Beam Resist for Ultrahigh Integration of Nanometer Lateral-Scale Organic Electronic Devices, SCIENTIFIC REPORTS, 7, 20170627
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