SHINICHI NISHIZAWA

Last Updated :2025/05/09

Affiliations, Positions
Graduate School of Advanced Science and Engineering, Associate Professor

Educational Activity

Course in Charge

  1. 2025, Liberal Arts Education Program1, 1Term, Introductory Seminar for First-Year Students

Research Activities

Academic Papers

  1. Standard Cell Structure and Diffusion Reordering for Block Area Reduction in Double Diffusion Break FinFET Process, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2025
  2. Multithread implementation for Open Cell Timing Characterizer, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E108A(3), 525-528, 2025
  3. De-correlation and De-bias Post-processing Circuits for True Random Number Generator, IEEE Transactions Circuits and Systems-I: Regular Papers, 71(11), 5187-5199, 2024
  4. Area Efficient Approximate 4-2 Compressor and Probability-based Error Adjustment for Approximate Multiplier, IEEE Transactions Circuits and Systems-II: Express Briefs, 70(5), 1714-1718, 2023
  5. libretto: An Open Cell Timing Characterizer for Open Source VLSI Design, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E106, 2022
  6. NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(12), 5568-5581, 2021
  7. Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E105(3), 487-496, 2021
  8. Supplemental PDK for ASAP7 using Synopsys Flow, IPSJ Transactions on System LSI Design Methodology (T-SLDM), 14, 24-26, 2021
  9. Universal NBTI Compact Model Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement, IPSJ Transactions on System LSI Design Methodology (T-SLDM), 13, 56-64, 2020
  10. Analog circuit design methodology utilizing a structure of thin BOX FDSOI, IEICE Electronics Express (ELEX), 16(5), 2018
  11. Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E101(12), 2271-2279, 2018
  12. Design Methodology for Variation Tolerant D-Flip-Flop using Regression Analysis, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E101(12), 2222-2230, 2018
  13. Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell, IPSJ Transactions on System LSI Design Methodology (T-SLDM), 8, 131-135, 2015
  14. A Ring Oscillator with Calibration Circuit for On-Chip Measurement of Static IR-drop, IEEE Transactions on Semiconductor Manufacturing, 26(3), 306-313, 2013
  15. Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E96(12), 2499-2504, 2013

Invited Lecture, Oral Presentation, Poster Presentation

  1. An EDA Based Side-Channel Attack Flamework for Netlists, Ryoma Katsube, Shinichi Nishizawa, Tomoaki Ukezono, SoutheastCon, 2025, Without Invitation, English
  2. Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Double Diffusion Break FinFET Process, Shinichi Nishizawa, Shinji Kimura, International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA), 2024, Without Invitation, English
  3. A Latch-based Stochastic Number Generator for Stochastic Computing of Extended Naïve Bayesian, Ruilin Zhang, Xiaoyang Jun, Jiawei Liu, Xingyu Wang, Shufan Xu, Kunyang Liu, Shinichi Nishizawa, Kiichi Niitsu, Hirofumi Shinohara, International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA), 2024, Without Invitation, English
  4. Area Efficient Approximate 4-2 Compressor and Probability-based Error Adjustment for Approximate Multiplier, Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura,, International Symposium on Circuits and Systems (ISCAS), 2023, Without Invitation, English
  5. Evaluation of Application-Independent Unbiased Approximate Multipliers for Quantized Convolutional Neural Networks, Mingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura, International Symposium on System-on-Chip Conference (SOCC), 2023, Without Invitation, English
  6. Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction, Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura, International Symposium on System-on-Chip Conference (SOCC), 2023, Without Invitation, English
  7. An 8-Point Approximate DCT Design with Optimized Signed Digit Encoding, Zekun Wang, Shinichi Nishizawa, Shinji Kimura, International Symposium on System-on-Chip Conference (SOCC), 2023, Without Invitation, English
  8. A Hardware-Efficient Approximate Multiplier Combining Inexact Same-Weight N:2 Compressors and Remapping Logic with Error Recovery , Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura, International Symposium on System-on-Chip Conference (SOCC), 2023, Without Invitation, English
  9. Density Rule Aware Cell Library Deisgn for Design-Technology Co-optimization, Shinichi Nishizawa, Tohru Nakura, International Symposium on Quality Electronic Design (ISQED), 2022, Without Invitation, English
  10. Library characterizer for open-source VLSI design, Shinichi Nishizawa, Toru Nakura, The Workshop on Open-Source EDA Technology (WOSET), 2022, Without Invitation, English
  11. Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics, Shinichi Nishizawa,Kazuhito Ito, International Conference on Microelectronic Test Structures (ICMTS), 2020, Without Invitation, English
  12. Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits, A.K.M. Mahfuzul Islam, Shinichi Nishizawa, Yusuke Matsui, and Yoshinobu Ichida, International Symposium on Quality Electronic Design (ISQED), 2019, Without Invitation, English
  13. NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map, Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen and Hidetoshi Onodera, Design Automation Conference (DAC), 2019, Without Invitation, English
  14. Compact Modeling of NBTI Replicationg AC Stress / Recovery from a Single-shot Long-term DC Measurement, Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi, International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Without Invitation, English
  15. Register Minimization in Double Modular Redundancy Design with Soft Error Correction by Replay, Yuya Kitazawa, Shinichi Nishizawa, Kazuhito Ito, Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), 2019, Without Invitation, English
  16. Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing, Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa and Hidetoshi Onodera, Internatioinal Conference on Computer Aided Design (ICCAD), 2020, Without Invitation, English
  17. Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution, Yuto Ishihara, Shinichi Nishizawa and Kazuhito Ito, Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2018, Without Invitation, English
  18. Process Variation Aware D-Flip-Flop Design using Regression Analysis, Shinichi Nishizawa and Hidetoshi Onodera, International Symposium on Quality Electronic Design (ISQED), 2018, Without Invitation, English
  19. Process Variation Estimation using A Combination of Ring Oscillator Delay and FlipFlop Retention Characteristics, Takuma Konno, Shinichi Nishizawa and Kazuhito Ito, International Conference on Microelectronic Test Structures (ICMTS), 2018, Without Invitation, English
  20. Register-Bridge Architecture and its Application to Multiprocessor Systems, Takafuji Fujii, Shinichi Nishizawa, Kazuhito Ito, Workshop on Synthesis And System Integration of Mixed Information technologies, 2016, Without Invitation, English
  21. An Impact of Process Variation on Supply Voltage Dependence of Logic Path Delay Variation, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, IEEE International Symposium on VLSI Design Automation and Test (VLSI-DAT), 2015, Without Invitation, English
  22. Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2014, Without Invitation, English
  23. Design Methodology of Process Variation Tolerant D-Flip-Flops for Low Voltage Circuit Operation, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, IEEE International System-On-Chip Conference (SoCC), 2014, Without Invitation, English
  24. Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage Operation, Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara and Hidetoshi Onodera, IEEE International System-On-Chip Conference (SoCC), 2014, Without Invitation, English
  25. An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2013, Without Invitation, English
  26. Analysis and Comparison of XOR Cell Structures for Low Voltage Circuit Design, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, IEEE International Symposium on Quality Electronic Design (ISQED), 2013, Without Invitation, English
  27. Ring Oscillator with Calibration Circuit for Accurate On-Chip IR-drop Measurement, Shinichi Nishizawa, Hidetoshi Onodera, IEEE International Conference on Microelectronics Test Structure (ICMTS), 2012, Without Invitation, English
  28. A Standard Cell Optimization Method for Near-Threshold Voltage Operations, Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara and Hidetoshi Onodera, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2012, Without Invitation, English
  29. A Flexible Structure of Standard Cell and Its Optimization Method for Near-Threshold Voltage Operation, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, IEEE International Conference on Computer Design (ICCD), 2012, Without Invitation, English
  30. An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera, IEEE/ACM International Workshop on Variability Modeling and Characterization (VMC), 2012, Without Invitation, English
  31. Modeling of Random Telegraph Noise under Circuit Operation - Simulation and Measurement of RTN-induced delay fluctuation, Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi and Hidetoshi Onodera, International Symposium on Quality Electronic Design (ISQED), 2011, Without Invitation, English
  32. The Impact of RTN on Performance Fluctuation in CMOS Logic Circuits, Kyosuke Ito, Takahi Matsumoto, Shinichi Nishizawa Hiroki Sunagawa, Kazutoshi Kobayashi and Hidetoshi Onodera, International Reliability Physics Symposium (IRPS), 2011, Without Invitation, English
  33. Modeling of Random Telegraph Noise under Circuit Operation- Simulation and Measurement of RTN-induced Delay Fluctuation, Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi and Hidetoshi Onodera, IEEE/ACM International Workshop on Variability Modeling and Charactorization (VMC), 2010, Without Invitation, English
  34. Extraction of Variability Sources from Within-die Random Delay Variation, Shuichi Fujimoto, Islam A.K.M Mahfzul, Shinichi Nishizawa and Hidetoshi Onodera, International Workshop on Design for Manufacturability & Yield (DFM&Y), 2010, Without Invitation, English
  35. Variability Characterization Using an RO-array Test Structure and Its Impact on Design, Shinichi Nishizawa, Hidetoshi Onodera, IEEE workshop on Design for Manufacturability and Yield (DFM&Y), 2010, Without Invitation, English