SHINICHI NISHIZAWA

Last Updated :2025/06/19

Affiliations, Positions
Graduate School of Advanced Science and Engineering, Associate Professor
Web Site
https://github.com/snishizawa
E-mail
nishizawahiroshima-u.ac.jp

Basic Information

Research Fields

  • Informatics;Computing Technologies;Computer system

Research Keywords

  • Very Large Scale Integration (VLSI)
  • Computer-Aided Design (CAD)
  • Electronic Design Automation (EDA)
  • Standard Cell Library

Educational Activity

Course in Charge

  1. 2025, Liberal Arts Education Program1, 1Term, Introductory Seminar for First-Year Students

Research Activities

Academic Papers

  1. An EDA Based Side-Channel Attack Flamework for Netlists, SoutheastCon, 20250301
  2. ★, Multithread Implementation of Open Source Library Characterizer, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E108.A(3), 525-528, 20250301
  3. ★, De-correlation and De-bias Post-processing Circuits for True Random Number Generator, IEEE Transactions Circuits and Systems-I: Regular Papers, 71(11), 5187-5199, 20240711
  4. A Latch-based Stochastic Number Generator for Stochastic Computing of Extended Naïve Bayesian, 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings, 20240401
  5. Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Double Diffusion Break FinFET Process, 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings, 20240401
  6. A Hardware-Efficient Approximate Multiplier Combining Inexact Same-Weight N:2 Compressors and Remapping Logic with Error Recovery , International Symposium on System-on-Chip Conference (SOCC), 20230901
  7. Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction, International Symposium on System-on-Chip Conference (SOCC), 20230901
  8. Evaluation of Application-Independent Unbiased Approximate Multipliers for Quantized Convolutional Neural Networks, International Symposium on System-on-Chip Conference (SOCC), 20230901
  9. An 8-point Approximate DCT Design with Optimized Signed Digit Encoding, International System on Chip Conference, 2023-September, 20230901
  10. Area Efficient Approximate 4-2 Compressor and Probability-based Error Adjustment for Approximate Multiplier, International Symposium on Circuits and Systems (ISCAS), 20230501
  11. ★, Area Efficient Approximate 4-2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier, IEEE Transactions on Circuits and Systems II: Express Briefs, 70(5), 1714-1718, 20230501
  12. ★, libretto: An Open Cell Timing Characterizer for Open Source VLSI Design, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E106A(3), 551-559, 20230301
  13. ★, NCTUcell: A DDA-and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(12), 5568-5581, 20221201
  14. Library characterizer for open-source VLSI design, The Workshop on Open-Source EDA Technology (WOSET), 20221101
  15. Density Rule Aware Cell Library Deisgn for Design-Technology Co-optimization, International Symposium on Quality Electronic Design (ISQED), 20220401
  16. ★, Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E105(3), 487-496, 20211201
  17. ★, Supplemental PDK for ASAP7 using synopsys flow, IPSJ Transactions on System LSI Design Methodology, 14, 24-26, 20210101
  18. MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2020-November, 20201102
  19. Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics, International Conference on Microelectronic Test Structures (ICMTS), 20200401
  20. ★, Universal NBTI compact model replicating AC stress/recovery from a single-shot long-term DC measurement, IPSJ Transactions on System LSI Design Methodology, 13, 56-64, 20200101
  21. Register Minimization in Double Modular Redundancy Design with Soft Error Correction by Replay, Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), 20191001
  22. Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, 305-309, 20190701
  23. NCTUcell: A DDA-aware cell library generator for FinFET structure with implicitly adjustable grid map, Proceedings - Design Automation Conference, 20190602
  24. Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits, International Symposium on Quality Electronic Design (ISQED), 20190301
  25. Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E101(12), 2271-2279, 20181201
  26. ★, Design methodology for variation tolerant d-flip-flop using regression analysis, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E101A(12), 2222-2230, 20181201
  27. ★, Analog circuit design methodology utilizing a structure of thin BOX FDSOI, IEICE Electronics Express (ELEX), 16(5), 20181101
  28. Process variation estimation using a combination of ring oscillator delay and FlipFlop retention characteristics, IEEE International Conference on Microelectronic Test Structures, 2018-March, 97-101, 20180312
  29. Process variation aware D-Flip-Flop design using regression analysis, Proceedings - International Symposium on Quality Electronic Design, ISQED, 2018-March, 88-93, 20180309
  30. Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution, Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 20180301
  31. Pin Accessibility Evaluating Model for Improving Routability of VLSI Designs, IEEE International System-On-Chip Conference (SoCC), 20170601
  32. Register-Bridge Architecture and its Application to Multiprocessor Systems, Workshop on Synthesis And System Integration of Mixed Information technologies, 20161001
  33. An impact of process variation on supply voltage dependence of logic path delay variation, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, 20150528
  34. ★, Layout generator with flexible grid assignment for area efficient standard cell, IPSJ Transactions on System LSI Design Methodology, 8, 131-135, 20150201
  35. Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation, International System on Chip Conference, 42-47, 20141105
  36. Variation-aware Flip-Flop energy optimization for ultra low voltage operation, International System on Chip Conference, 17-22, 20141105
  37. Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation, International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 20140301
  38. ★, A ring oscillator with calibration circuit for on-chip measurement of static IR-drop, IEEE Transactions on Semiconductor Manufacturing, 26(3), 306-313, 20130815
  39. Analysis and comparison of XOR cell structures for low voltage circuit design, Proceedings - International Symposium on Quality Electronic Design, ISQED, 703-708, 20130705
  40. An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay, International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 20130301
  41. ★, Standard cell structure with flexible P/N well boundaries for near-threshold voltage operation, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E96-A(12), 2499-2507, 20130101
  42. A flexible structure of standard cell and its optimization method for near-threshold voltage operation, Proceedings - IEEE International Conference on Computer Design, 235-240, 20121201
  43. An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay, IEEE/ACM International Workshop on Variability Modeling and Characterization (VMC), 20121101
  44. A Standard Cell Optimization Method for Near-Threshold Voltage Operations, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 20120901
  45. Ring oscillator with calibration circuit for accurate on-chip IR-drop measurement, IEEE International Conference on Microelectronic Test Structures, 3-8, 20120524
  46. The Impact of RTN on Performance Fluctuation in CMOS Logic Circuits, International Reliability Physics Symposium (IRPS), 20120401
  47. Modeling of Random Telegraph Noise under Circuit Operation - Simulation and Measurement of RTN-induced delay fluctuation, International Symposium on Quality Electronic Design (ISQED), 20110301
  48. Modeling of Random Telegraph Noise under Circuit Operation- Simulation and Measurement of RTN-induced Delay Fluctuation, IEEE/ACM International Workshop on Variability Modeling and Charactorization (VMC), 20101001
  49. Variability Characterization Using an RO-array Test Structure and Its Impact on Design, IEEE Workshop on Design for Manufacturability and Yield (DFM&Y), 20100601
  50. Extraction of Variability Sources from Within-die Random Delay Variation, IEEE Workshop on Design for Manufacturability and Yield (DFM&Y), 20100601

External Funds

Acceptance Results of Competitive Funds

  1. KAKENHI, 2016, 2018
  2. KAKENHI, 2017, 2019
  3. KAKENHI, 2018, 2020
  4. KAKENHI, 2021, 2024
  5. KAKENHI, 2024, 2027
  6. KAKENHI, 2025, 2028

Social Activities

History as Committee Members

  1. IPSJ, Special Interest Group on System and LSI Design Methodology, Committee Member, 2015, 2018, IPSJ, Special Interest Group on System and LSI Design Methodology
  2. SASIMI Orgnization Committee (Presentation), 2016, 2018, SASIMI Workshop
  3. IEICE VLD (VLSI Design Technologies) Committee Member, 2018, 2025, IEICE VLD (VLSI Design Technologies)
  4. IPSJ, Trans, SLDM, Editorial Member, 2020, 2023, IPSJ, Special Interest Group on System and LSI Design Methodology
  5. SASIMI Orgnization Committee (TPC Sec.), 2021, 2023, SASIMI Workshop
  6. ASP-DAC Orgnization Committee, 2021, ASP-DAC
  7. VLSI-TSA TPC Member, 2022, VLSI-TSA
  8. IEICE ICD (IC Design) Committee Member, 2023, IEICE ICD (IC Design)
  9. IEICE ICD (IC Design) Trans. Special Section on Solid-State Circuits Design - Architecture, Circuit, Device and Design Methodology, Editorial Member, 2023, IEICE ICD (IC Design)
  10. IPSJ, Special Interest Group on System and LSI Design Methodology, Committee Member, 2025, IPSJ, Special Interest Group on System and LSI Design Methodology
  11. SASIMI TPC subcommittee chair (physical design), 2025, SASIMI Workshop