Tetsushi Koide

Last Updated :2024/07/05

Affiliations, Positions
Research Institute for Nanodevice and Bio Systems, Associate Professor
Web Site
https://research-er.jp/researchers/view/164117
https://nrid.nii.ac.jp/ja/nrid/1000030243596/
http://www.RNBS.hiroshima-u.ac.jp/koide/
https://goo.gl/K8jBCn
https://goo.gl/RLsQEN
https://goo.gl/3nrqn3
http://www.seis.hiroshima-u.ac.jp/index.php?id=111
E-mail
koidehiroshima-u.ac.jp
Other Contact Details
"1-4-2, KAGAMIYAMA, HIGASHI-HIROSHIMA, HIROSHIMA, 739-8527, JAPAN", Japan
TEL : (+81)824-24-6265 FAX : (+81)824-24-3499
Self-introduction
I am conducting research on medical image (cancer) diagnosis support (CAD) systems, artificial intelligence information integration (LSI) systems, and agricultural support systems using IoT. If you would like to know about my research project, please search "Tetsushi Koide Hiroshima University" in Google Search Engine

Basic Information

Major Professional Backgrounds

  • 2001/05/01, The University of Tokyo, VLSI Design and Education Center (VDEC), Visiting Researcher
  • 2004/04/01, Hiroshima University, Department of Semiconductor Electronics and Integration Sciences, Associate Professor
  • 2000/04/01, 2001/03/31, Hiroshima University, Faculty of Engineering, Visiting Associate Professor
  • 1999/04/01, 2000/03/31, Hiroshima University, Faculty of Engineering, Associate Professor
  • 1999/03/01, 1999/03/31, Hiroshima University, Faculty of Engineering, Associate Professor
  • 1992/04/01, 1999/02/28, Hiroshima University, the Faculty of Engineering, Research Associate
  • 1996/04/01, 1996/10/09, Yuge National College of Maritime Technology, Visiting Assistant Professor
  • 2001/04/01, Hiroshima University, Research Center for Nanodevices and Systems, Associate Professor
  • 1999/04/01, 2001/03/31, The University of Tokyo, VLSI Design and Education Center (VDEC), Associate Professor

Educational Backgrounds

  • Hiroshima University, Graduate School, Division of Engineering, System Engineering, Japan, 1990/04, 1992/03
  • Hiroshima University, Faculty of Engineering, Japan, 1986/04, 1990/03

Academic Degrees

  • Doctor Engineering, Hiroshima University
  • Master of Engineering, Hiroshima University

Educational Activity

  • [Bachelor Degree Program] School of Engineering : Cluster 2(Electrical, Electronic and Systems Engineering) : Program of Electronic Devices and Systems
  • [Master's Program] Graduate School of Advanced Science and Engineering : Division of Advanced Science and Engineering : Quantum Matter Program
  • [Doctoral Program] Graduate School of Advanced Science and Engineering : Division of Advanced Science and Engineering : Quantum Matter Program

In Charge of Primary Major Programs

  • Program of Electrical,Systems and Information Engineering
  • Electrical, Computer, and Systems Engineering
  • Electronic Devices and Systems

Research Fields

  • Informatics;Computing Technologies;Computer system
  • Informatics;Computing Technologies;High performance computing
  • Informatics;Human informatics;Perceptual information processing
  • Informatics;Human informatics;Intelligent informatics
  • Complex systems;Biomedical engineering;Medical systems
  • Complex systems;Biomedical engineering;Biomedical engineering / Biomaterial science and engineering
  • Engineering;Electrical and electronic engineering;Electron device / Electronic equipment
  • Engineering;Electrical and electronic engineering;Electronic materials / Electric materials
  • Engineering;Electrical and electronic engineering;Control engineering / System engineering
  • Agricultural sciences;Agroengineering;Agricultural environmental engineering / Agriculturalinformation engineering
  • Informatics;Frontiers of informatics;Life / Health / Medical informatics

Research Keywords

  • Design Automation|Cache
  • Real Time Processing|LSI
  • LSI|Image Compression
  • Registor File|Image Segmentation
  • Digital and Analog Circuits|VLSI
  • Vector Quantaization|Image Segmentation
  • LSI|Associative Memory
  • CAD|Multi-Port Memory
  • LSI|Associative Memory
  • Learning|Motion Estimation

Affiliated Academic Societies

  • Asia and South Pacific Design Automation Conference(ASPDAC'00), 2000
  • Asia and South Pacific Design Automation Conference(ASPDAC'01), 2001
  • Asia and South Pacific Design Automation Conference(ASPDAC'02)
  • Asia and South Pacific Design Automation Conference(ASPDAC'03)
  • Asia and South Pacific Design Automation Conference(ASPDAC'04)
  • Asia and South Pacific Design Automation Conference(ASPDAC'05), 2004, 2005
  • Asia and South Pacific Design Automation Conference(ASPDAC'97), 1996
  • Asia and South Pacific Design Automation Conference(ASPDAC'98), 1997
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'00), 2000
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'01), 2001
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'03)
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'04)
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'06)
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), 1997
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'98), 1998
  • IPSJ, 1994
  • IEICE, 1996, 2001
  • IEEE
  • ACM

Educational Activity

Course in Charge

  1. 2024, Undergraduate Education, 2Term, CMOS Logic Circuit Design
  2. 2024, Undergraduate Education, Year, Graduation Thesis
  3. 2024, Graduate Education (Master's Program) , First Semester, Seminar on Electronics A
  4. 2024, Graduate Education (Master's Program) , Second Semester, Seminar on Electronics B
  5. 2024, Graduate Education (Master's Program) , Academic Year, Academic Presentation in Electronics
  6. 2024, Graduate Education (Master's Program) , 1Term, Exercises in Electronics A
  7. 2024, Graduate Education (Master's Program) , 2Term, Exercises in Electronics A
  8. 2024, Graduate Education (Master's Program) , 3Term, Exercises in Electronics B
  9. 2024, Graduate Education (Master's Program) , 4Term, Exercises in Electronics B
  10. 2024, Graduate Education (Master's Program) , 3Term, System LSI Design Engineering
  11. 2024, Graduate Education (Master's Program) , Academic Year, Advanced Study in Quantum Matter
  12. 2024, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Quantum Matter
  13. 2024, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Quantum Matter

Research Activities

Academic Papers

  1. Parallel Software Encryption of AES Algorithm by Using CAM-Based Massive-Parallel SIMD Matrix Core for Mobile Accelerator, JOURNAL OF ADVANCES IN INFORMATION TECHNOLOGY, 14(2), 355-362, 202304
    Link to Paper Search Results by DOI
  2. Implementation of Floating-Point Arithmetic Processing on Content Addressable Memory-Based Massive-Parallel SIMD matriX Core, IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, 18(4), 546-558, 202304
    Link to Paper Search Results by DOI
  3. A Method for Diagnosis Support of Colonoscopy Based on NICE Classification Using Deep Learning, Proceedings of the 27th Symposium on Sensing through Image Processing (SSII2021), 1-5, 20210609
  4. A Method for Diagnosis Support of Colonoscopy Based on JNET Classification Using Deep Learning, Proceedings of the 27th Symposium on Sensing through Image Processing (SSII2021), 1-5, 20210609
  5. A Method of Sweat Drop Detection Using Deep Learning for Impression Mold Method of Sweat Function Examination, Proceedings of the 27th Symposium on Sensing through Image Processing (SSII2021), 1-6, 20210609
  6. Automatic Analysis Method of Skinfolds and Furrows Using Deep Learning for Impression Mold Method of Sweat Function Test, Proceedings of the 27th Symposium on Sensing through Image Processing (SSII2021), 1-5, 20210609
  7. PARALLEL ISOLATION CHANNELS OF SOLUBLE SOLID REAGENTS FOR LONG TERM-USE NUTRIENT ANALYZER, The 25th International Conference on Miniaturized Systems for Chemistry and Life Sciences (microTAS 2021), 1507-1508, 20211010
  8. Floating-point arithmetic of content addressable memory-based massive-parallel SIMD matrix core, Proc. of RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 20210301
  9. Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model, IEEE ELECTRON DEVICE LETTERS, 30(8), 873-875, 200908
    Link to Paper Search Results by DOI
  10. Measurement-Based Ring Oscillator Variation Analysis, IEEE DESIGN & TEST OF COMPUTERS, 27(5), 6-13, 2010
    Link to Paper Search Results by DOI
  11. An associative memory-based learning model with an efficient hardware implementation in FPGA, EXPERT SYSTEMS WITH APPLICATIONS, 38(4), 3499-3513, 201104
    Link to Paper Search Results by DOI
  12. Analysis of Within-Die Complementary Metal-Oxide-Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM, JAPANESE JOURNAL OF APPLIED PHYSICS, 50(4), 201104
    Link to Paper Search Results by DOI
  13. Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E94D(9), 1742-1754, 201109
    Link to Paper Search Results by DOI
  14. A Scalable Massively Parallel Processor for Real-Time Image Processing, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 46(10), 2363-2373, 201110
    Link to Paper Search Results by DOI
  15. An Architecture for Compact Associative Memories with Deca-ns Nearest-Match Capability up to Large Distances, 170-171, 20010201
  16. ★, Compact associative-memory architecture with fully-parallel search capability for the minimum Hamming distance, IEEE Journal of Solid-State Circuits, 37(2), 218-227, 20020201
  17. A RISC Architecture for high-speed execution of genetic algorithms, Proc. 2001 Genetic and Evolutionary Computation Conference=, 1338-1345, 20010701
  18. A parallel genetic algorithm with adaptive adjustment of genetic parameters, Proc. 2001 Genetic and Evolutionary Computation Conference=, 679-686, 20010701
  19. A performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion, Proc. of the Tenth Workshop on Synthesis And System Integration of MIxed Technologies, 226-233, 20011001
  20. An iterative improvement circuit partitioning algorithm under path delay constraints, IEICE Transactions on Fundamentals of Electronics= Communications and Computer Sciences, E83-A(12), 2569-2576, 20001201
  21. Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 99-104, 20000101
  22. ★, Genetic algorithm accelerator GAA-II, Proc. of Asia and South Pacific Design Automation Conference 2000, 9-10, 20000101
  23. An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 3, 65-68, 20000501
  24. An architecture for compact associative memories with deca-ns nearest-match capability up to large distances, 2001 IEEE International Solid-State Circuits Conference (ISSCC 2001)= Dig. of Tech. Paper, 44, 170-171, 20010201
  25. A timing-driven global routing with pin assignment, block reshaping, and positioning for building block layout, IEICE Transactions on Fundamentals of Electronics= Communications and Computer Sciences, E81-A(12), 2476-2484, 19981201
  26. A timing-driven floorplanning algorithm with the Elmore delay model for building block layout, INTEGRATION= the VLSI journal, 27(1), 57-76, 19990101
  27. GAA : A VLSI genetic algorithm accelerator with on-the-fly adaptation of crossover operations, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 2, 268-271, 19980501
  28. Adapting parameters based on pedigree of individuals in a genetic algorithm, Proc. of the Symposium on Genetic Algorithms, 510-517, 19980701
  29. A circuit partitioning algorithm under path delay constraints, Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, WT32-1.1, 113-116, 19981101
  30. A performance-driven global routing algorithm with wire-sizing and buffer-insertion, WT32-3.1, 121-124, 19981101
  31. Solving the rectangular problem by an adaptive GA based on sequence-pair, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 181-184, 19990101
  32. An LSI implementation of an adaptive genetic algorithm with on-the-fly crossover operator selection, 37-40, 19990101
  33. A timing-driven floorplanning algorithm with the Elmore delay model for building block layout, 403-414, 19970801
  34. Timing-driven pin assignment with improvement of cell placement in standard cell layout, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 3, 1552-1555, 19970601
  35. ★, On-the-fly crossover adaptation of genetic algorithm, Proc. of Genetic Algorithms in Engineering Systems : Innovations and Applications, 197-202, 19970901
  36. A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 577-583, 19980201
  37. Solving the capacitor placement problem in a radial distribution system using an adaptive genetic algorithm, Proc. of the 5th International Conference on Parallel Problem Solving From Nature, 1028-1037, 19980301
  38. Mixed planar and H-V over-the-cell routing for standard cells with nonuniform over-the-cell routing capacities, IEICE Transactions on Information and Systems, E79-D(10), 1419-1430, 19961001
  39. An efficient timing-driven global routing method for standard cell layout, IEICE Transactions on Information and Systems, E79-D(10), 1410-1418, 19961001
  40. ★, Pin assignment with global routing for VLSI building block layout, IEEE Trans. on Computer-Aided Design on Integrated Circuits and Systems, 15(12), 1575-1583, 19961201
  41. A timing-driven placement algorithm with the Elmore delay model for row based VLSIs, INTEGRATION= the VLSI journal, 24(1), 53-77, 19970101
  42. A timing-driven global routing algorithm considering channel density minimization for standard cell layout, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 4, 424-427, 19960501
  43. An optimal pin assignment algorithm with improvement of cell placement in standard cell layout, Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, 381-384, 19961101
  44. Par-POPINS: A timing driven parallel placement method with the Elmore delay model for row based VLSIs, Proc. of Asia and South Pacific Design Automation Conference, 133-140, 19970101
  45. A standard cell global routing algorithm with net selection for over-the-cell routing, Electronics and Communication in Japan part2, 78(12), 102-115, 19951201
  46. A three-layer over-the-cell multi-channel router for a new cell model, INTEGRATION= the VLSI journal, 21(3), 171-189, 19960301
  47. A verification algorithm for logic circuits with internal variables, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 1920-1921, 19950401
  48. An MCM routing algorithm considering crosstalk, Proc. of 1995 IEEE International Symposium on Circuits and Systems, 211-214, 19950401
  49. A new system partitioning method under performance and physical constraints for multi-chip modules, Proc. of Asia and South Pacific Design Automation Conference, 119-126, 19950801
  50. ★, A new performance driven placement method with the Elmore delay model for row based VLSIs, Proc. of Asia and South Pacific Design Automation Conference, 405-412, 19950801
  51. A three-layer over-the-cell multi-channel routing method for a new cell model, Proc. of Asia and South Pacific Design Automation Conference, 195-202, 19950801
  52. A floorplanning method with topological constraint manipulation in VLSI building block layout, IEICE Transactions on Fundamentals of Electronics= Communications and Computer Sciences, E77-A(12), 2053-2057, 19941201
  53. A graph bisection algorithm based on subgraph migration, IEICE Transactions on Fundamentals of Electronics= Communications and Computer Sciences, E77-A(12), 2039-2044, 19941201
  54. A floorplanning method with topological constraint manipulation, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 1, 165-168, 19940501
  55. Three-layer channel routing for standard cells with column-dependent variable over-the-cell routing capacities, Proc. of 1994 IEEE Custom Integrated Circuits Conference, 28.1.1-28.1.4, 19940501
  56. A systolic graph partitioning algorithm for VLSI design, Proc. of 1994 IEEE International Symposium on Circuits and Systems, 1, 225-228, 19940501
  57. An optimal channel pin assignment algorithm for hierarchical building-block layout design, IEICE Trans. on Fundamentals of Electronics= Communications and Computer Science, E76-A(10), 1636-1644, 19931001
  58. Gate array placement based on mincut partitioning with path delay constraints, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 2059-2062, 19930501
  59. A new global routing algorithm for over-the-cell routing in standard cell layouts, Proc. of European Design Automation Conference, 116-121, 19930901
  60. Optimal channel pin assignment with multiple intervals for building block layout, Proc. of European Design Automation Conference, 348-353, 19920901
  61. An integrated approach to pin assignment and global routing for VLSI building-block layout, Proc. of European Conference on Design Automation, 24-28, 19930201
  62. A performance-driven ?oorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion, Proc. Synthesis and System Integration of Mixed Technologies 2001, 226-233, 20010101
  63. A RISC processor for high-speed execution of genetic algorithms, Proc. 2001 Genetic and Evolutionary Computation Conference, 1338-1345, 20010701
  64. A parallel genetic algorithm with adaptive adjustment of genetic parameters, Proc. 2001 Genetic and Evolutionary Computation Conference, 679-686, 20010701
  65. An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints, IEICE Trans. Fundamentals, E83-A(12), 2569-2576, 20001201
  66. An adaptive genetic algorithm for VLSI ?oorplanning based on sequence-pair, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 65-68, 20000501
  67. Genetic algorithm accelerator GAA-II, Proc. 2000 Asia-South Paci?c Design Automation Conference, 9-10, 20000101
  68. Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer, Proc. 2000 Asia-South Paci?c Design Automation Conference, 99-104, 20000101
  69. A timing-driven ?oorplanning algorithm with the Elmore delay model for building block layout, INTEGRATION= the VLSI journal, 27, 57-76, 19990101
  70. An LSI implementation of an adaptive genetic algorithm with on-the-?y crossover operator selection, Proc. 2000 Asia-South Paci?c Design Automation Conference, 37-40, 19990101
  71. Solving the rectangular packing problem by an adaptive GA based on sequence pair, Proc. 2000 Asia-South Paci?c Design Automation Conference, 181-184, 19990101
  72. A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout, IEICE Trans. Fundamentals, E81-A(12), 2476-2484, 19981201
  73. A performance-driven global routing algorithm with wire-sizing and buffer-insertion, Proc. 1998 IEEE Asia-Paci?c Conference on Circuits and Systems, 121-124, 19981101
  74. A circuit partitioning algorithm under path delay constraints, Proc. 1998 IEEE Asia-Paci?c Conference on Circuits and Systems, 113-116, 19981101
  75. Solving the capacitor placement problem in a radial distribution system using an adaptive genetic algorithm, Proceedings of the 5-th Conference on Parallel Problem Solving from Nature, 510-517, 19980901
  76. Adapting parameters based on pedigree of individuals in a genetic algorithm, Proceedings of the Third Annual Genetic Programming Conference, 510-517, 19980701
  77. GAA: A VLSI genetic algorithm accelerator with on-the-?y adaptation of crossover operators, 2, 268-271, 19980501
  78. A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout, Proceedings of the Asia-South Pacific Design Automation Conference, 577-583, 19980101
  79. On-the-?y crossover adaptation of genetic algorithms, 197-202, 19970901
  80. A timing-driven ?oorplanning algorithm with the Elmore delay model for building block layout, 403-414, 19970801
  81. Timing-driven pin assignment with improvement of cell placement in standard cell layout, Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, 1552-1555, 19970601
  82. A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs, INTEGRATION= the VLSI journal, 24(1), 53-77, 19970101
  83. Pin assignment with global routing for VLSI building block layout, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 15(12), 1575-1583, 19961201
  84. An optimal pin assignment algorithm with improvement of cell placement in standard cell layout, Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, 381-384, 19961101
  85. A timing-driven global routing algorithm considering channel density minimization for standard cell layout, Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, 424-427, 19960501
  86. A three-layer over-the-cell multi-channel router for a new cell model, INTEGRATION= the VLSI journal, 21(3), 171-189, 19960101
  87. Mixed planar and H-V over-the-cell routing for standard cells with nonuniform over-thecell routing capacities, E79-D(10), 1419-1430, 19960101
  88. An effcient timing-driven global routing method for standard cell layout, E79-D(10), 1410-1418, 19960101
  89. A new performance driven placement method with the Elmore delay model for row based VLSIs, Proceedings of the Asia-South Paci?c Design Automation Conference, 405-412, 19950801
  90. A three-layer over-the-cell multi-channel routing method for a new cell model, Proceedings of the Asia-South Paci?c Design Automation Conference, 195-202, 19950801
  91. A new system partitioning method under performance and physical constraints for multichip modules, Proceedings of the Asia-South Paci?c Design Automation Conference, 119-126, 19950801
  92. A veri?cation algorithm for logic circuits with internal variables, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 1920-1923, 19950401
  93. An MCM routing algorithm considering crosstalk, Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, 211-214, 19950401
  94. A graph bisection algorithm based on subgraph migration, IEICE Trans. Fundamentals, E77-A(12), 2039-2044, 19941201
  95. A systolic graph partitioning algorithm for VLSI design, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, 225-228, 19940501
  96. A ?oorplanning method with topological constraint manipulation, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, 165-168, 19940501
  97. Three-layer channel routing for standard cells with column-dependent variable over-the-cell routing capacities, Proceedings of the IEEE 1994 Custom Integrated Circuits Conference, 643-646, 19940501
  98. An optimal channel pin assignment algorithm for hierarchical building-block layout design, IEICE Trans. Fundamentals, E76-A(10), 1636-1644, 19930101
  99. A new global routing algorithm for over-the-cell routing in standard cell layouts, 116-121, 19930901
  100. Gate array placement based on mincut partitioning with path delay constraints, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 2059-2062, 19930501
  101. An integrated approach to pin assignment and global routing for VLSI building-block layout, Proceedings of the European Conference on Design Automation with the European Event in ASIC Design, 24-28, 19930201
  102. An optimal channel pin assignment with multiple intervals for building block layout, 348-353, 19920901
  103. A Performance-Driven Floorplanning Method with Interconnect Performance Estimation, IEICE Transactions on Fundametals of Electronics= Communications and Computer Sciences, E85-A(12), 2775-2784, 20021201
  104. Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance, Proc. of 2002 Symposium on VLSI Circuits, 252-255, 20020601
  105. Digital gray-scale/color image-segmentation architecture for cell-network-based real-time applications, Proc. of The 2002 International Technical Conference On Circuits/Systems= Computers and Communications (ITC-CSCC2003), 670-673, 20020701
  106. Real-time segmentation architecture of gray-scale/color motion pictures and digital test-chip implementation, Proc. of the 2002 IEEE Asia-Pacific Conference on ASICs (AP-ASIC2002), 237-240, 20020801
  107. Low-complexity, highly-parallel color motion-picture segmentation architecture for compact digital CMOS implementation, 1994 International Conf. on Solid State Devices and Materials, 242-243, 20020901
  108. Fully parallel nearest Manhattan-distance-search memory with large reference-pattern number, Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (SSDM2002), 254-255, 20020901
  109. A nearest-Hamming-distance search memory with fully parallel mixed digital-analog match circuitry, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 591-592, 20030101
  110. Optimized Bank-Based Multi-Port Memories through a Hierarchical Multi-Bank Structure, Proc. of the 11th Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI 2003), 323-330, 20030401
  111. High Access Bandwidth Multi-Port-Cache Design with Compact Hierarchical 1-Port-Bank Structure, Proc. of the 11th Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI 2003), 394-400, 20030401
  112. An Associative Memory for Real-Time Applications Requiring Fully Parallel Nearest Manhattan-Distance-Search, Proc. of the 11th Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI 2003), 200-205, 20030401
  113. A High-speed and Low Power Hierarchical Multi-Port Cache, Proc. of the 6th International Symposium on low-power and high-speed chip (COOL Chips VI), in press, 20030401
  114. CMOS Test Chip for a High-Speed Digital Image-Segmentation Architecture with Pixel-Parallel Processing, Proc. of The 2002 International Technical Conference On Circuits/Systems= Computers and Communications (ITC-CSCC2003), in press, 20030701
  115. A Novel Hierarchical Multi-port Cache, Proc. of ESSCIRC2003, in press, 20030901
  116. Compact Associative-Memory Architecture with Fully-Parallel Search Capability for the Minimum Hamming Distance, IEEE Journal of Solid-State Circuits, 37(2), 218-227, 20020201
  117. Fully-Parallel Pattern-Matching Engine with Dynamic Adaptability to Hamming or Manhattan Distance, 1999 Symposium on VLSI Circuits Dig. of Technical Papers, 252-255, 20020601
  118. Digital Gray-Scale/Color Image-Segmentation Architecture for Cell-Network-Based Real-Time Applications, Proc. 1996 International Technical Conference on Circuits/Systems= Computers and Communications(ITC-CSCC), 670-673, 20020601
  119. Real-Time Segmentation Architecture of Gray-Scale/Color Motion Pictures and Digital Test-Chip Implementation, Proc. of the 2002 IEEE Asia-Pacific Conference on ASICs (AP-ASIC2002), 237-240, 20020701
  120. Low-Complexity, Highly-Parallel Color Motion-Picture Segmentation Architecture for Compact Digital CMOS Implementation, 1994 International Conf. on Solid State Devices and Materials, 242-243, 20020901
  121. Fully Parallel Nearest Manhattan-Distance-Search Memory with Large Reference-Pattern Number, 254-255, 20020901
  122. A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 591-592, 20030101
  123. An Associative Memory for Real-Time Applications Requiring Fully-Parallel Nearest Manhattan-Distance Search, 200-205, 20030401
  124. Optimized Bank-Based Multi-Port Memories through a Hierarchical Multi-Bank Structure, 323-330, 20030401
  125. High Access Bandwidth Multi-Port-Cache Design with Compact Hierarchical 1-Port-Bank Structure, 394-400, 20030401
  126. High-Speed and Low-Power Multi-Port-Cache, Proceedings of COOL Chips VI, 76, 20030501
  127. A Novel Hierarchical Multi-Port Cache, in press, 20030901
  128. Low-Power Real-Time Region-Growing Image-Segmentation in 0.35mm CMOS due to Subdivided-Image and Boundary-Active-Only Architectures, 146-147, 20030901
  129. Combined Data/Instruction Cache with Bank-Based Multi-Port Architecture, Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials (SSDM2003), 150-151, 20030901
  130. A Hierarchical 512-Kbit SRAM with 8 Ports in 130nm CMOS, Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials (SSDM2003), 152-153, 20030901
  131. Associative Memory with Fully Parallel Nearest-Manhattan-Distance Search for Low-Power Real-Time Single-Chip Applications, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), in press, 20040101
  132. Bank-Type Multiport Register File for Highly-Parallel Processors, Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials (SSDM2003), 400-401, 20030901
  133. 350nm CMOS Test-Chip for Architecture Verification of Real-Time QVGA Color-Video Segmentation at the 90nm Technology Node, Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC2004), in press, 20040101
  134. Compact 12-Port Multi-Bank Register File Test-Chip in 0.35um CMOS for Highly Parallel Processors, Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC2004), in press, 20040101
  135. A 143MHz, 1.1W, 32mm2, 4.5Mb dynamic ternary CAM in 130nm embedded DRAM technology with pipelined hierarchical searching and row/column-shift redundancy architecture, 2004 IEEE International Solid-State Circuits Conference (ISSCC 2004)= Dig. of Tech. Paper, 208-209, 20040201
  136. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessor, The INSTITUTE of ELECTRONICS= INFORMATION AND COMMUNICATION ENGINEERS., in press, 20040401
  137. Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation, IEICE Transactions on Information and Systems, in press, 20040401
  138. Analog-Circuit-Component Optimization with Genetic Algorithm, The 2004 IEEE International Midwest Symposium on Circuits and Systems, 1, 489-492, 20040401
  139. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors, J87-D-I(3), 350-363, 20040301
  140. Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation, E87-D(2), 500-503, 20040201
  141. Distributed versus centralized crossbar function for realizing bank-based multiport memories, IEE Electronics Letters, 40(2), 101-1-3, 20040101
  142. Distributed-crossbar architecture for area-efficient combined data/instruction caches with multiple ports, IEE Electronics Letters, 40(3), 160-162, 20040201
  143. A Cost-Efficient High-Performance Dynamic TCAM with Pipelined Hierarchical Searching and Shift Redundancy Architecture, IEEE Journal of Solid-State Circuits, 39, in press, 20050401
  144. A Cost-Efficient Dynamic Ternary CAM in 130nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture, 1999 Symposium on VLSI Circuits Dig. of Technical Papers, 83-84, 20040601
  145. Proposition and Evaluation of a Bank-Based Multi-Port Memory with Blocking Network, Proceedings of the 2004 International Technical Conference on Circuits/Systems= Computers and Communications (ITC-CSCC2004), 6C2L-3-1-6C2L-3-4, 20040701
  146. Low-Power Design for Real-Time Image Segmentation LSI and Compact Digital CMOS Implementation, Proceedings of the 2004 IEEE Asia-Pacific Conference on ASICs (AP-ASIC2004), 432-433, 20040801
  147. Low Power Bank-based Multi-port SRAM Design due to Bank Standby Mode, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 1, 569-572, 20040701
  148. Reference-Pattern Learning and Optimization from an Input-Pattern Stream for Associative-Memory-Based Pattern-Recognition System, Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2004), 1, 561-564, 20040701
  149. Optimized Multi-Stage Minimum-Distance-Search Circuit with Feedback Stabilization for Fully-Parallel Associative Memories, Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2004), 1, 161-164, 20040701
  150. Analog-Circuit-Component Optimization with Genetic Algorithm, Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2004), 1, 489-492, 20040701
  151. A Hierarchical Placement Method for Standard Cell Layout Based on Wire Length Driven Clustering, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, III, 423-426, 20040701
  152. Digital Low-Power Real-Time Video Segmentation by Region Growing, 1994 International Conf. on Solid State Devices and Materials, 138-139, 20040901
  153. Automatic Pattern-Learning Architecture Based on Associative Memory and Short/Long Term Storage Concept, Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials (SSDM2004), 362-363, 20040901
  154. Bank-Type Associative Memory for High-Speed Nearest Manhattan Distance Search in Large Reference-Pattern Space, Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials (SSDM2004), 360-361, 20040901
  155. Highly Efficient Switch Architecture Based on Banked Memory with Multiple Ports, 12th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI2004), 491-498, 20041001
  156. Real-Time Segmentation of Large-Scale Images by Pipeline Processing with Small-Size Cell Network, 12th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI2004), 95-102, 20041001
  157. A Numerical Approach for Snake Models and Implementation with an FPGA Architecture, in press, 20041001
  158. A Low-Power Video Segmentation LSI with Boundary-Active-Only Architecture, in press, 20051001
  159. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors, Systems and Computers in Japan, in press, 20050401
  160. Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh, IEICE Trans. on Electronics, E88-C, in press, 20050401
  161. Object Tracking in Video Pictures based on Image Segmentation and Pattern Matching, Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005), in press, 20050501
  162. CAM-based VLSI Architecture for Huffman Coding with Real-time Optimization of the Code Word Table, Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005), in press, 20050601
  163. Design of Superscalar Processor with Multi-Bank Register File, Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005), in press, 20050601
  164. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors, J87-D-I(4), 350-363, 20040401
  165. Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation, E87-D(2), 500-503, 20040201
  166. Distributed against centralized crossbar function for realizing bank-based multiport memories, IEE Electronics Letters, 40(2), 101-103, 20040101
  167. Distributed-crossbar architecture for area-efficient combined data/instruction caches with multiple ports, IEE Electronics Letters, 40(3), 160-162, 20040201
  168. A Cost-Efficient High-Performance Dynamic TCAM With Pipelined Hierarchical Searching and Shift Redundancy Architecture, IEEE Journal of Solid-State Circuits, 40(1), 245-253, 20050101
  169. Core-level magnetic-circular-dichroism study of an Fe single crystal, Fe-Pt alloys, and an Fe/Pt multilayer, Physical Review B, 53(13), 8219-8222, 19940401
  170. Magnetic circular dichroism study of KBr and RbBr, Journal of Electron Spectroscopy and Related Phenomena, 78, 247-250, 19960501
  171. Magnetic circular dichroism of Excitons in KI and RbI, Journal of Electron Spectroscopy and Related Phenomena, 78, 295-298, 19960501
  172. Magnetic circular dichroism in CoS_2_ at the L_2,3_ and M_2,3_ core edges, Journal of Electron Spectroscopy and Related Phenomena, 78, 255-258, 19960501
  173. Core-level magnetic circular dichroism in Fe_7_S_8_ and Fe_7_Se_8_, Journal of Electron Spectroscopy and Related Phenomena, 78, 259-262, 19960501
  174. Core-level magnetic circular dichroism in Co/Pt multilayers with varying Co-layer thicknesses, Journal of Electron Spectroscopy and Related Phenomena, 78, 271-274, 19960501
  175. Magneto-optical Kerr spectra of epitaxially grown Fe(001) and Fe(110) films in the range 1.5-10eV, Journal of Magnetism and Magnetic Materials, 177-181, 1251-1252, 19980101
  176. Photoemission magnetic circular dichroism study of the ferromagnetic transition-metal oxide SrRuO_3_, Journal of Electron Spectroscopy and Related Phenomena, 92(1-3), 41-44, 19980501
  177. A compact molecular-beam epitaxy apparatus for in situ soft X-ray magnetic circular dichroism experiments, Journal of Synchrotron Radiation, 5, 1038-1041, 19980501
  178. Perpendicular magnetic anisotropy caused by interfacial hybridization via enhanced orbital moment in Co/Pt multilayers: magnetic circular X-ray dichroism study, Physical Review Letters, 81(23), 5229-5232, 19981201
  179. Soft X-ray magnetic circular dichroism in La_1-x_Sr_x_MnO_3_ and SrFe_1-x_Co_x_O_3_, Journal of Magnetic Society of Japan, 23, 341-345, 19990101
  180. Soft X-ray magnetic circular dichroism in 3d transition-metal chalcogenides, Journal of Magnetic Society of Japan, 23, 504-506, 19990101
  181. Magnetic anisotropy, interfacial hybridization, and orbital magnetic moment in Co/Pt multilayers, Journal of Magnetic Society of Japan, 34, 578-580, 19990101
  182. A Cost-Efficient Dynamic Ternary CAM in 130nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture, 1999 Symposium on VLSI Circuits Dig. of Technical Papers, 83-84, 20030601
  183. CMOS Test Chip for a High-Speed Digital Image-Segmentation Architecture with Pixel-Parallel Processing, Proc. 1996 International Technical Conference on Circuits/Systems= Computers and Communications(ITC-CSCC), 284-287, 20030501
  184. Low-Power Real-Time Region-Growing Image-Segmentation in 0.35um CMOS due to Subdivided-Image and Boundary-Active-Only Architectures, 146-147, 20030901
  185. Bank-Type Multiport Register File for Highly-Parallel Processors, 400-401, 20030901
  186. Combined Data/Instruction Cache with Bank-Based Multi-Port Architecture, 152-153, 20030901
  187. A Hierarchical 512-Kbit SRAM with 8 Read/Write Ports in 130nm CMOS, 150-151, 20030901
  188. Compact 12-Port Multi-Bank Register File Test Chip in 0.35um CMOS for Highly Parallel Processors, 551-552, 20040101
  189. Associative Memory with Fully Parallel Nearest-Manhattan-Distance Search for Low-Power Real-Time Single-Chip Applications, 543-544, 20040101
  190. A 143MHz, 1.1W, 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture, 208-209, 20040201
  191. Proposition and Evaluation of a Bank-Based Multi-Port Memory with Blocking Network, Proc. 1996 International Technical Conference on Circuits/Systems= Computers and Communications(ITC-CSCC), 6C2L-3, 20040501
  192. Low-Power Design for Real-Time Image Segmentation LSI and Compact Digital CMOS Implementation, Proceedings of the 2004 IEEE Asia-Pacific Conference on ASICs (AP-ASIC2004), 432-433, 20040501
  193. Low Power Bank-based Multi-port SRAM Design due to Bank Standby Mode, 569-572, 20040701
  194. Reference-Pattern Learning and Optimization from an Input-Pattern Stream for Associative-Memory-Based Pattern-Recognition System, 561-564, 20040701
  195. Optimized Multi-Stage Minimum-Distance-Search Circuit with Feedback Stabilization for Fully-Parallel Associative Memories, 161-164, 20040701
  196. Analog-Circuit-Component Optimization with Genetic Algorithm, 489-492, 20040701
  197. Digital Low-Power Real-Time Video Segmentation by Region Growing, 1994 International Conf. on Solid State Devices and Materials, 138-139, 20040901
  198. Automatic Pattern-Learning Architecture Based on Associative Memory and Short/Long Term Storage Concept, 362-363, 20040901
  199. Bank-Type Associative Memory for High-Speed Nearest Manhattan Distance Search in Large Reference-Pattern Space, 360-361, 20040901
  200. Highly Efficient Switch Architecture Based on Banked Memory with Multiple Ports, 491-498, 20041001
  201. Real-Time Segmentation of Large-Scale Images by Pipeline Processing with Small-Size Cell Network, 95-102, 20041001
  202. A Numerical Approach for Snake Models and Implementation with an FPGA Architecture, 1-6, 20041101
  203. A Low-Power Video Segmentation LSI with Boundary-Active-Only Architecture, D13-D14, 20050101
  204. Linear and magnetic circular dichroism in the Ce 4d X-ray absorption spectroscopy of CeRh/sub 3/B/sub 2/, Physica B (Netherlands), 186-188, 83-85, 19930401
  205. Soft-X-ray linear-dichroism and magnetic-circular-dichroism studies of CeRh/sub 3/B/sub 2/: large crystal-field splitting and anomalous ferromagnetism, Phys. Rev. B= Condens. Matter (USA), 51(20), 13952-13960, 19950401
  206. In-situ DC oxygen-discharge cleaning system for optical elements., Review of Scientific Instruments, 60(7), 2034-2037, 19890401
  207. Core-level magnetic circular dichroism in Fe_7_S_8_ and Fe_7_Se_8_, Journal of Electron Spectroscopy and Related Phenomena, 78, 259-262, 19960401
  208. Magnetic circular X-ray dichroism in Fe_7_S_8_ and Fe_7_Se_8_, Japanese Journal of Applied Physics, 79(8), 5707-, 19960401
  209. Correlating Microscopic and Macroscopic Variation with Surface-Potential Compact Model, IEEE Electron Device Letters, 30(8), 873-875, 20090801
  210. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, Jpn. J. Appl. Phys., 48(4), 04C078, 20090401
  211. Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor, IEICE Trans. on Electronics, E91-C(9), 1409-1418, 20080901
  212. 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words, IEICE Trans. on Electronics, E90-C(11), 2157-2160, 20071101
  213. Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor, IEICE Trans. on Information & Systems, E90-D(8), 1312-1215, 20070801
  214. Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories, IEICE Trans. on Fundamentals, E90-A(6), 1240-1243, 20070601
  215. Mixed Digital-Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search, Jpn. J. Appl. Phys., 46(4B), 2231-2237, 20070401
  216. A 2-stage-pipelined 16 Port SRAM with 590 Gbps Random Access Bandwidth and Large Noise Margin, IEICE Electronics Express, 4(2), 21-25, 20070116
  217. Scalable FPGA/ASIC Implementation Architecture for Parallel Table-lookup Coding Using Multi-ported Content Addressable Memory, IEICE Trans. on Information & Systems, E90-D(1), 346-354, 20070101
  218. Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer, IEICE Trans. on Information & Systems, E90-D(1), 334-345, 20070101
  219. A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC, IEICE Trans. on Electronics, E89-C(11), 1612-1619, 20061101
  220. Performance Evaluation of Superscalar Processor with Multi-Bank Register File and an Implementation Result, WSEAS Transactions on Computer, 9(5), 1993-2000, 20060901
  221. Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video Segmentation, IEICE Trans. on Information & Systems, E89-D(3), 1299-1302, 20060301
  222. Evaluation of Bank based Multi-port Memory Architecture with Blocking Network, Wiley, Systems & Computers in Japan, 37(2), 22-33, 20060201
  223. Pixel-Parallel Digital-CMOS Implementation of Image-Segmentation by Region Growing, IEE Proc. Circuits, Devices & Systems, 152(12), 579-589, 20051201
  224. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors, Systems & Computers in Japan, 36(9), 1-13, 20050901
  225. A CAM-based signature-matching co-processor with application-driven power-reduction features, IEICE Trans. on Electronics, E88-C(6), 1332-1342, 20050601
  226. Evaluation of a Bank-based Multi-port Memory Architecture with Blocking Network, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, J88-A(4), 498-510, 20050401
  227. Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh, IEICE Trans. on Electronics, E88-C(4), 622-629, 20050401
  228. Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model, 20090601
  229. VLSI Design of a Handwritten-Character Learning and Recognition system based on Associative Memory, 161-166, 20090327
  230. Analysis of Process Variations in 90-nm CMOS Technology with Ring Oscillators, 446-449, 20090327
  231. Improved Region-Growing Image-Segmentation Algorithm Based on HSV Color Space, 167-171, 20090328
  232. A Ternary Multi-Ported Content Addressable Memory Architecture utilizing Asynchronous Multiple Search-Operation Technology, 224-229, 20090328
  233. Low Power and Area Efficient Image Segmentation VLSI Architecture Using 2-Dimensional Pixel-Block Scanning, 441-444, 20090228
  234. Grouping Method based on Feature Matching for Tracking and Recognition of Complex Objects, 421-424, 20090228
  235. Low-Power Image-Segmentation VLSI Design Based on a Pixel-Block Scanning Architecture, 474-475, 20081008
  236. Static-Noise-Margin Analysis of Major SRAM-Cell Type under Production Variation for a 90nm CMOS Process, 261-265, 20071017
  237. Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories, 32-37, 20071015
  238. An Effective Parallel Coding Architecture Utilizing Characteristics of Multimedia Application, 74-80, 20071015
  239. Area Efficieant Fully Parallel Associative Memory with Fast Winner Search Capability, 38-41, 20071016
  240. Acceleration of Advanced Encryption Standard (AES) Processing on a CAM Enhanced Super Parallel SIMD Processor, 26-31, 20071016
  241. Associative Memory Design Realizing Reference-Pattern Recognition and Learning based on Short/Long-Term Storage Concept, 21-25, 20071016
  242. Performance Evaluation of Region-Growing Image Segmentation Using Two-Dimensional Image-Block Scanning, 69-73, 20071016
  243. A 0.6-Tbps, 16-Port SRAM Design with 2-Stage-Pipeline and Multi-Stage-Sensing Scheme, 320-323, 20070912
  244. CAM Enhanced Super Parallel SIMD Processor with High-Speed Pattern Matching Capability, 803-806, 20070824
  245. Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine, 525-528, 20070501
  246. Developing a Reliable Learning Model for Cognitive Classification Tasks Using an Associative Memory, 214-219, 20070401
  247. Huffman Encoding Architecture with Self-Optimizing Performance and Multiple CAM-Match Utilization, CA2.3, 20061101
  248. Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline, 1299-1302, 20061201
  249. Application of Multi-ported CAM for Parallel Coding, 1681-1684, 20061201
  250. Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search, 1311-1324, 20061201
  251. Image-Scan Video Segmentation Architecture and FPGA Implementation, 590-591, 20060901
  252. Nearest Euclidean-Distance-Search Associative Memory Architecture with Fully Parallel Mixed Digital-Analog Match Circuitry, 282-283, 20060901
  253. Multi-Bank Register File for Increased Performance of Highly-Parallel Processors, 154-157, 20060901
  254. Performance Evaluation of Superscalar Processor with Multi-Bank Register File Using SPEC2000, Proceedings of the 10th WSEAS International Conference on COMPUTERS, 1062-1067, 20060701
  255. A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA, 2702-2708, 20060701
  256. Minimum Euclidean Distance Associative Memory Architecture with Fully-Parallel Search Capability, 350-354, 20060401
  257. Multi-Object Tracking VLSI Architecture using Image-Scan based Region Growing and Feature Matching, 5575-5578, 20060501
  258. Image Segmentation and Pattern Matching Based FPGA/ASIC Implementation of Real-Time Object Tracking, 176-181, 20060101
  259. Highly Parallel Huffman Encoding by Exploiting Multiple Matches in Content Addressable Memory, 313-316, 20051101
  260. Image-Scan Architecture for Efficient FPGA/ASIC Implementation of Video-Segmentation by Region Growing, 301-304, 20051101
  261. A Parallel Hardware Design for Parametric Active Contour Models, 609-613, 20050901
  262. An LSI hardware design for online character recognition using associative memory, 464-467, 20050801
  263. Multi-Port CAM based VLSI Architecture for Huffman Coding with Real-time Optimized Code Word Table, 55-58, 20050801
  264. A Parallel Hardware Design for Snake Models with an FPGA Architecture, 146-150, 20050501
  265. CAM-based VLSI Architecture for Huffman Coding with Real-time Optimization of the Code Word Table, 5202-5205, 20050501
  266. Object Tracking in Video Pictures based on Image Segmentation and Pattern Matching, 3215-3218, 20050501
  267. Design of Superscalar Processor with Multi-Bank Register File, 3507-3510, 20050501
  268. Superscalar Processor with Multi-Bank Register File, 3-12, 20050101
  269. Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 37(2), 218-227, 200202
    Link to Paper Search Results by DOI
  270. A performance-driven floorplanning method with interconnect performance estimation, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A(12), 2775-2784, 200212
    Link to Paper Search Results by DOI
  271. Distributed against centralised crossbar function for realising bank-based multiport memories, ELECTRONICS LETTERS, 40(2), 101-103, 20040122
    Link to Paper Search Results by DOI
  272. Efficient video-picture segmentation algorithm for cell-network-based digital CMOS implementation, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E87D(2), 500-503, 200402
    Link to Paper Search Results by DOI
  273. Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports, ELECTRONICS LETTERS, 40(3), 160-162, 20040205
    Link to Paper Search Results by DOI
  274. Embedded low-power dynamic TCAM architecture with transparently scheduled refresh, IEICE TRANSACTIONS ON ELECTRONICS, E88C(4), 622-629, 200504
    Link to Paper Search Results by DOI
  275. A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 40(1), 245-253, 200501
    Link to Paper Search Results by DOI
  276. A CAM-based signature-matching co-processor with application-driven power-reduction features, IEICE TRANSACTIONS ON ELECTRONICS, E88C(6), 1332-1342, 200506
    Link to Paper Search Results by DOI
  277. Pixel-parallel digital CMOS implementation of image segmentation by region growing, IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 152(6), 579-589, 200512
    Link to Paper Search Results by DOI
  278. Evaluation of bank-based multiport memory architecture with blocking network, ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 89(6), 22-33, 2006
    Link to Paper Search Results by DOI
  279. Boundary-active-only adaptive power-reduction scheme for region-growing video-segmentation, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E89D(3), 1299-1302, 200603
    Link to Paper Search Results by DOI
  280. Mixed digital-analog associative memory enabling fully-parallel nearest Euclidean distance search, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(4B), 2231-2237, 200704
    Link to Paper Search Results by DOI
  281. A reliability-enhanced TCAM architecture with associated embedded DRAM and ECC, IEICE TRANSACTIONS ON ELECTRONICS, E89C(11), 1612-1619, 200611
    Link to Paper Search Results by DOI
  282. Real-time Huffman encoder with pipelined CAM-based data path and code-word-table optimizer, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 334-345, 200701
    Link to Paper Search Results by DOI
  283. Scalable FPGA/ASIC implementation architecture for parallel table-lookup-coding using multi-ported content addressable memory, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 346-354, 200701
    Link to Paper Search Results by DOI
  284. A 2-stage-pipelined 16 port SRAM with 590 Gbps random access bandwidth and large noise margin, IEICE ELECTRONICS EXPRESS, 4(2), 21-25, 20070125
    Link to Paper Search Results by DOI
  285. Realization of K-Nearest-Matches search capability in fully-parallel associative memories, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A(6), 1240-1243, 200706
    Link to Paper Search Results by DOI
  286. Acceleration of DCT processing with massive-parallel memory-embedded SIMD matrix processor, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(8), 1312-1315, 200708
    Link to Paper Search Results by DOI
  287. 4-port unified data/instruction cache design with distributed crossbar and interleaved cache-line words, IEICE TRANSACTIONS ON ELECTRONICS, E90C(11), 2157-2160, 200711
    Link to Paper Search Results by DOI
  288. Integration architecture of content addressable memory and massive-parallel memory-embedded SIMD matrix for versatile multimedia processor, IEICE TRANSACTIONS ON ELECTRONICS, E91C(9), 1409-1418, 200809
    Link to Paper Search Results by DOI
  289. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(4), 200904
    Link to Paper Search Results by DOI
  290. Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 47(6), 1448-1459, 201206
    Link to Paper Search Results by DOI
  291. Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal-Oxide-Semiconductor Technology Including Its Distance Dependences, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 201204
    Link to Paper Search Results by DOI
  292. High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 201204
    Link to Paper Search Results by DOI
  293. A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E95D(9), 2327-2338, 201209
    Link to Paper Search Results by DOI
  294. Quantitative identification of mucosal gastric cancer under magnifying endoscopy with flexible spectral imaging color enhancement, JOURNAL OF GASTROENTEROLOGY AND HEPATOLOGY, 28(5), 841-847, 201305
    Link to Paper Search Results by DOI
  295. A Computer System To Be Used With Laser-based Endoscopy for Quantitative Diagnosis of Early Gastric Cancer, JOURNAL OF CLINICAL GASTROENTEROLOGY, 49(2), 108-115, 201502
  296. Computer-aided diagnosis of colorectal polyp histology by using a real-time image recognition system and narrow-band imaging magnifying colonoscopy, GASTROINTESTINAL ENDOSCOPY, 83(3), 643-649, 201603
    Link to Paper Search Results by DOI
  297. Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition, ARTIFICIAL INTELLIGENCE IN MEDICINE, 68, 1-16, 201603
    Link to Paper Search Results by DOI
  298. Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition, PSYCHOLOGISCHE RUNDSCHAU, 68(1), 1-16, 201603
    Link to Paper Search Results by DOI
  299. Secure data processing with massive-parallel SIMD matrix for embedded SoC in digital-convergence mobile devices, IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, 12(1), 96-104, 201701
    Link to Paper Search Results by DOI
  300. Real-time Speed Limit Traffic Sign Detection System for Robust Automotive Environments, IEIE Transactions on Smart Processing and Computing, 4(5), 237-250, 2015
  301. Trade-off between speed and performance for colorectal endoscopic NBI image classification, Proc. SPIE 9413, Medical Imaging 2015, 94132D, 2015
  302. High Accuracy and Simple Real-Time Circle Detection on Low-Cost FPGA for Traffic-Sign Recognition on Advanced Driver Assistance System, roceeding of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), 1, 397-402, 2015
  303. Speed Traffic-Sign Number Recognition on Low Cost FPGA for Robust Sign Distortion and Illumination Conditions, Proceeding of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), 1, 421-426, 2015
  304. High Performance Feature Transformation Architecture based on Bag-of-Features in CAD system Colorectal Endoscopic Images, Proceeding of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), 1, 380-385, 2015
  305. Effective Diagnostic Image Segmentation with Pyramid Style Support Vector Machine for Colorectal Endoscopic Images, The 30th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2015), 1, 596-599, 2015
  306. Simple Yet Effective Two-Stage Speed Traffic Sign Recognition for Robust Vehicle Environments, The 30th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2015), 1, 420-423, 2015
  307. Image Segmentation of Pyramid Style Identifier based on Support Vector Machine for Colorectal Endoscopic Images, The 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC2015), 2997-3000, 2015
  308. Transfer Learning for Endoscopic Image Classification, Proc. of Korea-Japan joint Workshop on Frontiers of Computer Vision (FCV2016), 1, 258-262, 2016
  309. Computer-Aided Colorectal Tumor Classification in NBI Endoscopy Using CNN Features, Proc. of Korea-Japan joint Workshop on Frontiers of Computer Vision (FCV2016), 61-65, 2016
  310. Transfer Learning for Bag-of-Visual Words Approach to NBI endoscopic image classification, Proc. of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC2015), 785-788, 2015
  311. Trade-off between speed and performance for colorectal endoscopic NBI image classification, Proc. of SPIE Medical Imaging 2015, 9413-9416, 2015
  312. A Chip for Real-Time Segmentation Processing with Object-based Image-Scan Architecture, ITE technical report, 30(65), 73-78, 20061214
  313. Digital Low-Power Real-Time Video Segmentation by Region Growing, 2004, 138-139, 20040915
  314. Bank-Type Associative Memory for High-Speed Nearest Manhattan Distance Search in Large Reference-Pattern Space, 2004, 360-361, 20040915
  315. Automatic Pattern-Learning Architecture Based on Associative Memory and Short/Long Term Storage Concept, Extended Abstracts of SSDM2004, 2004, 362-363, 20040915
  316. Development of indwelling health monitoring system in the oral cavity, 2009(1), 25-28, 20090227
  317. The characteristic Evaluation of a CMOS Active Inductor Oscillator, 2011(47), 31-36, 20110630
  318. A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching, IEICE Trans. Inf. & Syst., 95(9), 2327-2338, 20120901
  319. A Feature Extraction Hardware Design in Computer-Aided Diagnosis System for Colorectal Endoscopic Images with NBI Magnification, 112(237), 13-18, 20121005
  320. A Dynamic Ternary CAM in 130nm CMOS Technology With Planar Complementary Capacitors, 111, 169-174, 20031023
  321. Construction and Evaluation of Bank-based Multi-port Memory using Blocking Network, 112, 271-276, 20031127
  322. Switch Architecture with Banked Multi-port Memory, IPSJ SIG Notes, 156, 37-42, 20040202
  323. Nearest Neighbor Searching A1gorithms for 2-Dimensional Arrays with Reconfigurable Buses, 49(0), 85-86, 19940920
  324. A Hypergraph k-way Partitioning Method Based on Dynamic Clustering, 49(0), 91-92, 19940920
  325. A Standard Cell Placement Method Based on Circuit Partitioning and Linear Programming, 49(0), 109-110, 19940920
  326. A Fault-Tolerant Leader Election Algorithm in an Anonymous Distributed System, 45(0), 63-64, 19920928
  327. A Distributed Algorithm Simulator for Networks with Arbitrary Topology and Communication Delay Model, 45(0), 279-280, 19920928
  328. A parameter setting method based on superiority of individuals in Genetic Algorithms, 55(0), 463-464, 19970924
  329. A Performance-Driven Global Routing Method with Wire-Widening and Buffer-Insertion, IPSJ SIG Notes, 97(17), 57-64, 19970214
  330. Performance Driven Standard Cell Placement Based on Nonlinear Programming, IPSJ SIG Notes, 94(15), 25-32, 19940204
  331. Multi-Port-Cache Design with Hierarchical Multi-Bank Memory, IEICE technical report. Dependable computing, 102(479), 169-174, 20021121
  332. Small-Area Multi-Port Register Files with Multi-Bank Structure, IEICE technical report. Dependable computing, 102(479), 175-180, 20021121
  333. Construction and Evaluation of Bank-based Multi-port Memory using Blocking Network, IEICE technical report. Dependable computing, 103(480), 241-246, 20031121
  334. A study of compact and multi-banks memory suitable for LSI, IEICE technical report. Circuits and systems, 102(161), 125-130, 20020620
  335. A Hierarchical Buffer Block Planning Method for ULSI Floorplanning, IEICE technical report. Computer systems, 101(473), 19-24, 20011122
  336. A Timing-Driven Standard-Cell Placement Method Based on Cell-Clustering and the New Placement Model, IEICE technical report. Computer systems, 101(473), 25-30, 20011122
  337. Minimum Cost Graph Bisection Based on Subgraph Migration, IEICE technical report. Theoretical foundations of Computing, 93(438), 41-48, 19940126
  338. An Efficient Timing-Driven Global Routing Method for Standard Cell Layout (Special Issue on Synthesis and Verification of Hardware Design), IEICE transactions on information and systems, 79(10), 1410-1418, 19961025
  339. Mixed Planar and H-V Over-the-Cell Routing for Standard Cells with Nonuniform Over-the-Cell Routing Capacities (Special Issue on Synthesis and Verification of Hardware Design), IEICE transactions on information and systems, 79(10), 1419-1430, 19961025
  340. Development of Compact and High-Speed Associative-Memories with Nearest-Match Capability for Hamming Distance, Proceedings of the IEICE General Conference, 2001(2), 20010307
  341. C-12-18 Associative-Memory-Based Automatic Learning Architecture for Integrated Recognition Systems, Proceedings of the IEICE General Conference, 2004(2), 20040308
  342. Comparison of the Hierarchical and Crossbar-based Architectures for the Construction Multibank Multiport Memory, Technical report of IEICE. VLD, 102(166), 37-42, 20020622
  343. A Fully-Parallel Associative Memory for Minimum-Manhattan-Distance-Search, Technical report of IEICE. VLD, 102(476), 181-186, 20021121
  344. Evaluation of Compact Multi-bank Memory using Multi-stage Interconnection Network, Technical report of IEICE. ICD, 102(686), 55-60, 20030228
  345. A Hierarchical Standard-Cell Placement Method Based on Wire Length-Driven Clustering, Technical report of IEICE. ICD, 103(478), 169-174, 20031121
  346. Access time and Chip area Evaluations of Bank based Multi-port Memory by Memory Generator, Technical report of IEICE. ICD, 104(250), 25-30, 20040812
  347. Pattern-Matching Engine Adaptable to Hamming or Manhattan Distance with Fully-Parallel Processing Capability, Technical report of IEICE. ICD, 102(234), 41-46, 20020718
  348. Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation(Image Processing and Video Processing), IEICE transactions on information and systems, 89(3), 1299-1302, 20060301
  349. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, Technical report of IEICE. ICD, 106(316), 39-44, 20061019
  350. Mixed Analog-Digital Fully-parallel Associative Memory with Differential Amplifier, Technical report of IEICE. ICD, 106(551), 31-36, 20070301
  351. A 128-Kbit, 16-Port SRAM Design with Multi-Stage-Sensing Scheme in 90-nm CMOS Technology, Technical report of IEICE. SDM, 107(194), 149-154, 20070816
  352. Acceleration of AES Encryption with CAM-Enhanced Massive-Parallel SIMD Matrix Processor, IEICE technical report. Computer systems, 107(276), 25-30, 20071018
  353. C-12-10 Associative Memory Design which Realizes Reference-Pattern Learning, Proceedings of the IEICE General Conference, 2007(2), 20070307
  354. C-12-11 Performance Evaluation of Image Segmentation LSI Using Two-Dimensional Block Scanning, Proceedings of the IEICE General Conference, 2007(2), 20070307
  355. Massive-Parallel Memory-Embedded SIMD Processor Architecture, IEICE technical report. Circuits and systems, 109(199), 59-64, 20090917
  356. Analysis of Process Variations by using Ring Oscillator, IEICE technical report. Circuits and systems, 109(199), 71-76, 20090917
  357. Image Segmentation Algorithm with Parameter Self-Adjustment Considering the Image Characteristic, IEICE technical report. Circuits and systems, 109(199), 77-82, 20090917
  358. Associative-Memory-Based LSI Architecture with Automatic Learning Functionality and Application to Handwritten-Character Recognition, IEICE technical report. Circuits and systems, 109(199), 91-96, 20090917
  359. Efficient Ternary Multiple Search-Operation Architecture based on Flexible Multi-Ported Content Addressable Memory and its Application, IEICE technical report. Circuits and systems, 109(199), 97-102, 20090917
  360. Realization of k-nearest-matches search capability in fully-parallel associative memories, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A(6), 1240-1243, 20070101
  361. Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer(Image Processing and Video Processing), IEICE transactions on information and systems, 90(1), 334-345, 20070101
  362. Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory(Image Processing and Video Processing), IEICE transactions on information and systems, 90(1), 346-354, 20070101
  363. 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words(Integrated Electronics), IEICE transactions on electronics, 90(11), 2157-2160, 20071101
  364. An Improved Face-Detection Method for a Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1, Technical report of IEICE. ICD, 109(336), 83-88, 20091207
  365. Associative-Memory-Based LSI with Adaptive-Learning Capability, Technical report of IEICE. ICD, 109(336), 89-94, 20091207
  366. Path Encoding Method for High Speed Frequency-Mapping Associative Memory, Technical report of IEICE. VLD, 111(40), 13-18, 20110511
  367. Object Detection Based on Haar-like Features with Massive-Parallel Memory-Embedded SIMD Matrix Processor, IEICE technical report. Computer systems, 112(237), 7-12, 20121005
  368. The Real-time Feature Extraction Architecture for Colorectal Endoscopic Images with NBI Magnification, IEICE technical report. Computer systems, 113(282), 25-30, 20131101
  369. Real-Time Speed Traffic-Sign Recognition Architecture Using Local Feature Value, IEICE technical report. Computer systems, 113(282), 43-48, 20131101
  370. Mixed Digital–Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search, Jpn J Appl Phys, 46(4), 2231-2237, 20070430
  371. Analysis of Within-Die Complementary Metal--Oxide--Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM, Jpn J Appl Phys, 50(4), 04DE05-04DE05-6, 20110425
  372. Switch Architecture with Banked Multi - port Memory, 2004(12), 37-42, 20040202
  373. Evolution of Non - Numerical Computation performance by Integration of Instruction and Trace Cache, 2003(119), 39-44, 20031127
  374. A Parallel Timing Driven Standard Cell Placement Method with Nonlinear Programming, 1995(119), 163-168, 19951214
  375. Construction and Evaluation of Bank - based Multi - port Memory using Blocking Network, 2003(120), 271-276, 20031127
  376. A Timing - Driven Hierarchical Global Routing Method wih Buffer - Insertion and Wire - Sizing for Multi - Layer ULSI, 1999(12), 105-112, 19990204
  377. A Hardware Algorithm for Graph Bisection, 1994(15), 17-24, 19940204
  378. A Floorplanning Method for Building Block Layout Based on the Manipulation of Topological Constraints, 1992(83), 33-40, 19921022
  379. Path Encoding Method for High Speed Frequency-Mapping Associative Memory, 2011(3), 1-6, 20110511
  380. High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme, Jpn J Appl Phys, 51(4), 04DE05-04DE05-6, 20120425
  381. Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification, 114(329), 33-38, 20141126
  382. Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images, 114(329), 39-44, 20141126
  383. Consideration for Acceleration of Feature Transformation based on the Bag-of-Features for Colorectal Endoscopic Images, 114(302), 7-12, 20141113
  384. An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System, 114(328), 27-32, 20141126
  385. Mixed digital-analog associative memory enabling fully-parallel nearest Euclidean distance search, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(4B), 2231-2237, 2007
  386. Realization of K-Nearest-Matches search capability in fully-parallel associative memories, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A(6), 1240-1243, 2007
  387. Small-Area Multi-Port Register Files with Multi-Bank Structure, Technical report of IEICE. VLD, 102(476), 175-180, 20021121
  388. An FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images, Proc. of The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 20161024
  389. Prototype Speed Limit Sign Recognition System Implementation on Rapid Prototyping Platform, Proc. of The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016
  390. Compact and High-Speed Hardware Feature Extraction Accelerator for Dense Scale-Invariant Feature Transform, Proc. of the 31th International Technical Conference on Circuits/Systems, Computers and Communications, 20160710
  391. A Hardware Accelerator for Bag-of Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images, Proc. of the 31th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2016), 20160710
  392. Discriminative subtree selection for NBI endoscopic image labeling, Proc. of The ACCV2016 workshop on mathematical and computational methods in biomedical imaging and image analysis (MCBMIIA2016), 20161124
  393. Development of a Real-time Colorectal Tumor Classification System for Narrow-band Imaging zoom-video endoscopy, Cornel University Library, CoRR, 9 pages, https://arxiv.org/abs/1612.05000v2., 2017
  394. Discriminative Subtree Selection for NBI Endoscopic Image Labeling, Proceedings of the International Workshop on Nanodevice Technologies 2017, pp. 82-83, Hiroshima, Japan, March 2, 2017., 20170302
  395. A Real-Time Visual Word Feature Transformation for Colorectal Endoscopic Images with NBI Magnification, Proceedings of the International Workshop on Nanodevice Technologies 2017, pp. 84-85, March 2, 2017., 20170302
  396. A Real-Time Type Identification based on Support Vector Machine for Colorectal Endoscopic Images with NBI Magnification, Proceedings of the International Workshop on Nanodevice Technologies 2017, pp. 86-87, March 2, 2017., 20170302
  397. A Real-Time D-SIFT Feature Extraction for Colorectal Endoscopic Images with NBI Magnification, Proceedings of th1e International Workshop on Nanodevice Technologies 2017, pp. 88-89, March 2, 2017
  398. Discriminative Subtree Selection for NBI Endoscopic Image Labeling, Proc. of International Symposium on Biomedical Engineering, pp.170-171, Nov. 10-11, 2016., 20170302
  399. A Real-Time Feature Extraction Method for Colorectal Endoscopic Images toward Computer-Aided Diagnosis, Proc. of International Symposium on Biomedical Engineering, pp.162-163, Nov. 10-11, 2016., 20161110
  400. A Real-Time Feature Transformation Method for Colorectal Endoscopic Images toward Computer-Aided Diagnosis, Proc. of International Symposium on Biomedical Engineering, pp.164-165, Nov. 10-11, 2016., 20161110
  401. A Real-Time Type Identification Method for Colorectal Endoscopic Images toward Computer-Aided Diagnosis, Proc. of International Symposium on Biomedical Engineering, pp.166-167, Nov. 10-11, 2016., 20161110
  402. An FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images, Proc. of The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, pp. 81-86, Oct. 24-25, 2016, 20161110
  403. Compact and High-Speed Hardware Feature Extraction Accelerator for Dense Scale-Invariant Feature Transform, Proc. of the 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2016), pp.596-599 , July 10-13, 2016, 20161110
  404. A Hardware Accelerator for Bag-of Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images, Proc. of the 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2016), pp.596-599 , July 10-13, 2016, 20160710
  405. Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor, IEICE Trans. Electron., 91(9), 1409-1418, 20080901
  406. A Type Identification Hardware Design in Computer-Aided Diagnosis System for Colorectal Endoscopic Images with NBI Magnification, 112(237), 19-24, 20121005
  407. Multi-Port-Cache Design with Hierarchical Multi-Bank Memory, Technical report of IEICE. VLD, 102(476), 169-174, 20021121
  408. Multi-Port-Cache Design with Hierarchical Multi-Bank Memory, Technical report of IEICE. ICD, 102(477), 169-174, 20021121
  409. Small-Area Multi-Port Register Files with Multi-Bank Structure, Technical report of IEICE. ICD, 102(477), 175-180, 20021121
  410. A Fully-Parallel Associative Memory for Minimum-Manhattan-Distance-Search, Technical report of IEICE. ICD, 102(477), 181-186, 20021121
  411. Construction and Evaluation of Bank-based Multi-port Memory using Blocking Network, Technical report of IEICE. ICD, 103(478), 241-246, 20031121
  412. Mixed Analog-Digital Fully-parallel Associative Memory with Differential Amplifier, Technical report of IEICE. VLD, 106(548), 31-36, 20070301
  413. Massive-Parallel Memory-Embedded SIMD Processor Architecture, IEICE technical report. Nonlinear problems, 109(200), 59-64, 20090917
  414. Analysis of Process Variations by using Ring Oscillator, IEICE technical report. Nonlinear problems, 109(200), 71-76, 20090917
  415. Image Segmentation Algorithm with Parameter Self-Adjustment Considering the Image Characteristic, IEICE technical report. Nonlinear problems, 109(200), 77-82, 20090917
  416. Efficient Ternary Multiple Search-Operation Architecture based on Flexible Multi-Ported Content Addressable Memory and its Application, IEICE technical report. Nonlinear problems, 109(200), 97-102, 20090917
  417. A Feature Extraction Hardware Design in Computer-Aided Diagnosis System for Colorectal Endoscopic Images with NBI Magnification, IEICE technical report. Computer systems, 112(237), 13-18, 20121005
  418. A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin, IEICE Electron. Express, 4(2), 21-25, 2007
  419. Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification, 114(328), 33-38, 20141126
  420. Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images, 114(328), 39-44, 20141126
  421. Scalable FPGA/ASIC implementation architecture for parallel table-lookup-coding using multi-ported content addressable memory, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 346-354, 2007
  422. A 2-stage-pipelined 16 port SRAM with 590 Gbps random access bandwidth and large noise margin, IEICE ELECTRONICS EXPRESS, 4(2), 21-25, 2007
  423. Acceleration of DCT processing with massive-parallel memory-embedded SIMD matrix processor, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(8), 1312-1315, 2007
  424. 4-port unified data/instruction cache design with distributed crossbar and interleaved cache-line words, IEICE TRANSACTIONS ON ELECTRONICS, E90C(11), 2157-2160, 2007
  425. Integration architecture of content addressable memory and massive-parallel memory-embedded SIMD matrix for versatile multimedia processor, IEICE TRANSACTIONS ON ELECTRONICS, E91C(9), 1409-1418, 2008
  426. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(4), 2009
  427. Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model, IEEE ELECTRON DEVICE LETTERS, 30(8), 873-875, 2009
  428. Measurement-Based Ring Oscillator Variation Analysis, IEEE DESIGN & TEST OF COMPUTERS, 27(5), 6-13, 2010
  429. An associative memory-based learning model with an efficient hardware implementation in FPGA, EXPERT SYSTEMS WITH APPLICATIONS, 38(4), 3499-3513, 2011
  430. Analysis of Within-Die Complementary Metal-Oxide-Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM, JAPANESE JOURNAL OF APPLIED PHYSICS, 50(4), 2011
  431. Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E94D(9), 1742-1754, 2011
  432. A Scalable Massively Parallel Processor for Real-Time Image Processing, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 46(10), 2363-2373, 2011
  433. Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal-Oxide-Semiconductor Technology Including Its Distance Dependences, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 2012
  434. High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 2012
  435. Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 47(6), 1448-1459, 2012
  436. A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E95D(9), 2327-2338, 2012
  437. Quantitative identification of mucosal gastric cancer under magnifying endoscopy with flexible spectral imaging color enhancement, JOURNAL OF GASTROENTEROLOGY AND HEPATOLOGY, 28(5), 841-847, 2013
  438. A Computer System To Be Used With Laser-based Endoscopy for Quantitative Diagnosis of Early Gastric Cancer, JOURNAL OF CLINICAL GASTROENTEROLOGY, 49(2), 108-115, 2015
  439. Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition, ARTIFICIAL INTELLIGENCE IN MEDICINE, 68, 1-16, 2016
  440. "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" (vol 68, pg 1, 2016), ARTIFICIAL INTELLIGENCE IN MEDICINE, 72, 83-83, 2016
  441. Secure data processing with massive-parallel SIMD matrix for embedded SoC in digital-convergence mobile devices, IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, 12(1), 96-104, 2017
  442. Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems, IEICE Trans. Inf. & Syst., 94(9), 1742-1754, 20110901
  443. Associative-Memory-Based LSI Architecture with Automatic Learning Functionality and Application to Handwritten-Character Recognition, IEICE technical report, 109(200), 91-96, 20090917
  444. A Type Identification Hardware Design in Computer-Aided Diagnosis System for Colorectal Endoscopic Images with NBI Magnification, IEICE technical report. Computer systems, 112(237), 19-24, 20121005
  445. The Real-time Type Classification Architecture for Colorectal Endoscopic Images with NBI Magnification, IEICE technical report. Computer systems, 113(282), 31-36, 20131108
  446. Pipeline Scanning Architecture for Traffic Sign Detection with Computation Reduction, IEICE technical report. Computer systems, 113(282), 37-42, 20131108
  447. Architecture Development for the Real-time Computer-Aided Diagnosis of Colorectal Endoscopic Images with NBI Magnification, IEICE technical report, 114(223), 1-6, 20140918
  448. An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System, Technical report of IEICE. VLD, 114(328), 27-32, 20141126
  449. Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification, Technical report of IEICE. VLD, 114(328), 33-38, 20141126
  450. Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images, Technical report of IEICE. VLD, 114(328), 39-44, 20141126
  451. An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System, IEICE technical report. Dependable computing, 114(329), 27-32, 20141126
  452. Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification, IEICE technical report. Dependable computing, 114(329), 33-38, 20141126
  453. Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images, IEICE technical report. Dependable computing, 114(329), 39-44, 20141126
  454. Hardware Oriented Speed Traffic-Sign Detection Algorithm for Robust Sign Distortion and Illumination Conditions, IEICE technical report. Computer systems, 114(302), 1-6, 20141113
  455. Consideration for Acceleration of Feature Transformation based on the Bag-of-Features for Colorectal Endoscopic Images, IEICE technical report. Computer systems, 114(302), 7-12, 20141113
  456. A Hierarchical Type Segmentation Algorithm based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images, IEICE technical report. Computer systems, 114(302), 13-18, 20141113
  457. Development of localized fertilization system for analyzing robustness of plants against environmental change, The Proceedings of the Symposium on Micro-Nano Science and Technology, 2017(0), PN-109, 2017
  458. Evaluation of the Effects of High Temperature on Growth and Grain Quality in Rice with Image Analysis, JJCS Extra, 246(0), 2018
  459. Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal--Oxide--Semiconductor Technology Including Its Distance Dependences, Jpn J Appl Phys, 51(4), 04DE03-04DE03-8, 20120425
  460. Application of Bank-Based Multiport Memory to the Microprocessor Caches, Technical report of IEICE. ICD, 105(2), 25-30, 20050408
  461. Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP), IEICE transactions on electronics, 88(4), 622-629, 20050401
  462. Multiple CAM Matches and Self-adapting Codeword Table for Optimized Real-time Huffman Encoding, ITE technical report, 30(65), 125-130, 20061214
  463. Memory-based Information Processing Systems, 30(65), 131-136, 20061214
  464. A Hierarchical Standard - Cell Placement Method Based on Wire Length - Driven Clustering, 2003(120), 199-204, 20031127
  465. Evolution of Non - Numerical Computation performance by Integration of Instruction and Trace Cache, IPSJ SIG Notes, 2003(119), 39-44, 20031127
  466. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessor, The Transactions of the Institute of Electronics,Information and Communication Engineers., 87(3), 350-363, 20040301
  467. A Hierarchical Standard-Cell Placement Method Based on Wire Length-Driven Clustering, IEICE technical report. Dependable computing, 103(480), 169-174, 20031128
  468. Detailed Multi-Bank Register File Design for Superscalar Processors, IEICE technical report. Computer systems, 104(241), 1-6, 20040725
  469. A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features(Integrated Electronics), IEICE transactions on electronics, 88(6), 1332-1342, 20050601
  470. Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation, IEICE Trans. on Information & Syst., D, 87(2), 500-503, 20040201
  471. C-12-10 Low Power Design for Cell-Network Based Image Segmentation LSI, Proceedings of the IEICE General Conference, 2004(2), 20040308
  472. A Hierarchical Standard-Cell Placement Method Based on Wire Length-Driven Clustering, Technical report of IEICE. VLD, 103(476), 169-174, 20031128
  473. Construction and Evaluation of Band-based Multi-port Memory using Blocking Network, Technical report of IEICE. VLD, 103(476), 241-246, 20031128
  474. Access time and Chip area Evaluations of Bank based Multi-port Memory by Memory Generator, Technical report of IEICE. SDM, 104(248), 25-30, 20040812
  475. Evaluation of a Bank Based Multi-port Memory Architecture with Blocking Network, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese edition) A, 88(4), 498-510, 20050401
  476. A 4.5Mb Dynamic TCAM with Pipelined Hierarchical Searching and Shift Redundancy Architecture, Technical report of IEICE. ICD, 104(24), 7-12, 20040416
  477. Banked Multiport Register File for Highly Parallel Processors, Technical report of IEICE. ICD, 104(521), 13-18, 20041216
  478. Evaluation of Branch Predictor for Unified Instruction Trace Cache, IPSJ SIG Notes, 2005(120), 75-80, 20051130
  479. A Chip for Real-Time Segmentation Processing with Object-based Image-Scan Architecture, IEICE technical report, 106(425), 73-78, 20061207
  480. Memory-based Information Processing Systems, IEICE technical report, 106(425), 131-136, 20061207
  481. A 128-Kbit, 16-Port SRAM Design with Multi-Stage-Sensing Scheme in 90-nm CMOS Technology, IEICE technical report, 107(195), 149-154, 20070816
  482. Acceleration of Multimedia Data Processing with CAM-Enhanced Massive-Parallel SIMD Matrix Processor, IEICE technical report, 107(276), 19-24, 20071018
  483. C-12-9 Implementation Method of Advanced Encryption Standard (AES) with Super Parallel SIMD Processor, Proceedings of the IEICE General Conference, 2007(2), 20070307
  484. C-12-20 An Efficient Implementation of Scan-Based Image Segmentation Architecture, Proceedings of the IEICE General Conference, 2008(2), 20080305
  485. C-12-27 Stability Evaluation of SRAM-cells in Small-Scale CMOS Technology, Proceedings of the IEICE General Conference, 2008(2), 20080305
  486. C-12-32 Implementation of AES Processing on Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1, Proceedings of the Society Conference of IEICE, 12, 2008
  487. C-12-31 A Parallel Face Detection on Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1 (2), Proceedings of the Society Conference of IEICE, 12, 2008
  488. C-12-30 A Parallel Face Detection on Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1 (1), Proceedings of the Society Conference of IEICE, 12, 2008
  489. Evaluation of a Hierarchical Bank Based Multi-Port Memory Architecture Using a Multiple Outlets Blocking Network as an Upper Hierarchy and a Non Blocking Network as a Lower Hierarchy, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese edition) A, 89(10), 774-789, 20061001
  490. Acceleration of DCT processing with massive-parallel memory-embedded SIMD matrix processor, IEICE Transactions on Information and Systems, E90-D(8), 1312-1315, 20070101
  491. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, Jpn J Appl Phys, 48(4), 04C078-04C078-4, 20090425
  492. A computer system to be used with laser-based endoscopy for quantitative diagnosis of early gastric cancer., Journal of clinical gastroenterology, 49(2), 2015
  493. Corrigendum to "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" [Artif. Intell. Med. 68 (March 2016) 1-16]., Artificial intelligence in medicine, 72, 2016
  494. A Hierarchical Standard-Cell Placement Method Based on Wire Length-Driven Clustering, 103(480), 169-174, 20031121
  495. Construction and Evaluation of Band-based Multi-port Memory using Blocking Network, 103(480), 241-246, 20031121
  496. An Integrated Method for Virtual Path Topology Design and Bandwidth Allocation Considering Multiple QoS Classes in ATM Networks, 1997(1), 161-168, 19970221
  497. A Floorplanning Method for Simultaneously Determining Module Placement and Global Routes Considering Buffer Insertion, 2000(111), 29-34, 20001129
  498. An Adaptive Genetic Algorithm with Sequence - Pair Representation of Solutions for VLSI Floorplanning, 1999(101), 119-126, 19991126
  499. A Hierarchical Buffer Block Planning Method for ULSI Floorplanning, 2001(117), 51-56, 20011128
  500. A Timing - Driven Standard - Cell Placement Method Based on Cell - Clustering and the New Placement Model, 2001(117), 57-62, 20011128
  501. A RISC Processor DLX-GA with Instruction Set Suitable for High-speed Execution of a Genetic Algorithm, Transactions of Information Processing Society of Japan, 44(2), 340-343, 20030215
  502. A Timing - driven Pin Assignment Algorithm with Improvement of Cell Placement in Standard Cell Layout, Transactions of Information Processing Society of Japan, 40(4), 1606-1617, 19990415
  503. An LSI Implementation of a Genetic Algorithm with Adaptive Selection of Crossover Operators, Transactions of Information Processing Society of Japan, 41(6), 1766-1776, 20000615
  504. A VLSI Floorplanning Method Based on an Adaptive Genetic Algorithm, Transactions of Information Processing Society of Japan, 43(5), 1361-1371, 20020515
  505. The proposal of integrted trace cache which combined instruction cache and trace cache, IPSJ SIG Notes, 2003(27), 79-84, 20030310
  506. A RISC Processor DLX - GA with Instruction Set Suitable for High - Speed Execution of a Genetic Algorithm, IPSJ SIG Notes, 2001(10), 65-70, 20010126
  507. Access Conflict Resolution Methods for Superscalar Processors with Multi - Bank Register File, IPSJ SIG Notes, 2002(112), 41-46, 20021127
  508. An MCM Routing Method for Via Minimization Considering Crosstalk, IPSJ SIG Notes, 1993(111), 31-38, 19931216
  509. A Formal Logic Verification Method Based on Circuit Partitioning Considering BDD Size, IPSJ SIG Notes, 1993(111), 47-54, 19931216
  510. A Three - Layer Over -the- Cell Channel Routing Method for a New Cell Model Considering Multi - Channel Routing, IPSJ SIG Notes, 1995(6), 121-128, 19950119
  511. A Circuit Partitioning Method Considering Performance and Physical Constraints for Multi - Chip Module Layout Design, IPSJ SIG Notes, 1995(6), 129-136, 19950119
  512. A Parallel Timing Driven Standard Cell Placement Method with Nonlinear Programming, IPSJ SIG Notes, 1995(119), 163-168, 19951214
  513. An MCM Routing Method Based on Layer Assignment Considering Timing and Crosstalk, IPSJ SIG Notes, 97(17), 65-72, 19970214
  514. A Circuit Partitioning Method under Path Delay Constraints, IPSJ SIG Notes, 1998(10), 25-32, 19980130
  515. A Rectilinear Steiner Tree Construction Algorithm with Simultaneous Buffer Insertion and Wire Sizing, IPSJ SIG Notes, 1998(10), 33-40, 19980130
  516. A Hardware Algorithm for Graph Bisection, IPSJ SIG Notes, 70, 17-24, 1994
  517. A Heuristic Algorithm for Hypergraph Partitioning Based on Dynamic Clustering, IPSJ SIG Notes, 1994(93), 7-12, 19941027
  518. A Timing Driven Standard Cell Global Routing Method, IPSJ SIG Notes, 1994(93), 31-36, 19941027
  519. An Algorithm for Optimal Pin Assignment in Standard Cell Layout Design, IPSJ SIG Notes, 96(16), 37-42, 19960209
  520. A Distributed Genetic Algorithm for Large Scale Circuit Partitioning, IPSJ SIG Notes, 1995(72), 9-16, 19950720
  521. A Timing-Driven Hierarchical Global Routing Method with Buffer-Insertion and Wire-Sizing for Multi-Layer ULSI, IPSJ SIG Notes, 99(12), 105-112, 19990204
  522. A Parameter Tuning Method Based on Meta - Heuristics for Genetic Algorithms, IPSJ SIG Notes, 1997(11), 17-24, 19970124
  523. An Adaptive Genetic Algorithm for Parameter Tuning Based on the Superiority of an Individual, IPSJ SIG Notes, 1998(6), 25-30, 19980123
  524. A Fully-Parallel Associative Memory for Minimum-Manhattan-Distance-Search, IEICE technical report. Dependable computing, 102(479), 181-186, 20021121
  525. A Dynamic Thernary CAM in 130nm CMOS Technology With Planar Complementary Capacitors, IEICE technical report. Image engineering, 103(384), 77-82, 20031017
  526. Gray-Scale/Color Image-Segmentation Architecture based on Cell-Network, IEICE technical report. Circuits and systems, 102(162), 49-54, 20020621
  527. Small-Area Multi-Port Register Files due to Bank Structure for Highly Parallel Processors, IEICE technical report. Circuits and systems, 102(163), 31-36, 20020622
  528. Comparison of the Hierarchical and Crossbar-based Architectures for the Construction Multibank Multiport Memory, IEICE technical report. Circuits and systems, 102(163), 37-42, 20020622
  529. A Hardware-Based Genetic Algorithm with Adaptive Selection of Crossover Operators : LSI Implementation and Its Evaluation, IEICE technical report. Computer systems, 97(524), 51-58, 19980130
  530. A Floorplanning Method for Simultaneously Determining Module Placement and Global Routes Considering Buffer Insertion, IEICE technical report. Computer systems, 100(476), 29-34, 20001123
  531. Adapting Genetic Operators and GA Parameters Based on Elite Degree of an Individual in a Genetic Algorithm, The Transactions of the Institute of Electronics,Information and Communication Engineers., 82(9), 1135-1143, 19990925
  532. A Coterie-Based Mutual Exclusion Algorithm for Distributed Systems allowing Multiple Process Failures at Arbitrary Time, The Transactions of the Institute of Electronics,Information and Communication Engineers., 83(8), 823-833, 20000825
  533. A Fault-Tolerant Distributed Mutual Exclusion Algorithm with Arbitrary Failures and Recoveries, IEICE technical report. Theoretical foundations of Computing, 96(398), 41-50, 19961206
  534. Distributed Algorithms for Updating Paths in a Dynamic Network, IEICE technical report. Theoretical foundations of Computing, 93(358), 11-20, 19931126
  535. A Timing-Driven Hierarchical Global Routing Method with Buffer-Insertion and Wire-Sizing for Multi-Layer ULSI, Technical report of IEICE. FTS, 98(585), 63-70, 19990205
  536. A heuristic algorithm for hypergraph partitioning based on dynamic clustering, Technical report of IEICE. FTS, 94(313), 7-12, 19941027
  537. A timing driven standard cell global routing method, Technical report of IEICE. FTS, 94(313), 31-36, 19941027
  538. The Processor IP for Research with Software Development Environment, Technical report of IEICE. FTS, 101(476), 121-126, 20011129
  539. An Integrated Method for Virtual Path Topology Design and Bandwidth Allocation Considering Multiple QoS Classes in ATM Networks, IEICE technical report. Information networks, 96(543), 161-168, 19970221
  540. A performance driven analog module layout generator, IEICE technical report. Circuits and systems, 93(432), 45-52, 19940121
  541. A Graph Bisection Algorithm Based on Subgraph Migration (Special Section on VLSI Design and CAD Algorithms), IEICE transactions on fundamentals of electronics, communications and computer sciences, 77(12), 2039-2044, 19941225
  542. A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout (Special Section on VLSI Design and CAD Algorithms), IEICE transactions on fundamentals of electronics, communications and computer sciences, 77(12), 2053-2057, 19941225
  543. A Performance-Driven Floorplanning Method with Interconnect Performance Estimation, IEICE transactions on fundamentals of electronics, communications and computer sciences, 85(12), 2775-2784, 20021201
  544. An Optimal Channel Pin Assignment Algorithm for Hierarchical Building-Block Layout Design (Special Section on VLSI Design and CAD Algorithms), IEICE transactions on fundamentals of electronics, communications and computer sciences, 76(10), 1636-1644, 19931025
  545. A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout, IEICE transactions on fundamentals of electronics, communications and computer sciences, 81(12), 2476-2484, 19981201
  546. An Adaptive Genetic Algorithm with Sequence-Pair Representation of Solutions for VLSI Floorplanning, IEICE technical report. Computer systems, 99(481), 81-88, 19991127
  547. A Survey on CAD Technologies of System-on-Silicon Era., The Journal of the Institute of Electronics,Information and Communication Engineers, 81(9), 903-907, 199809
  548. VLSI Chip Design and CAD Tools, Proceedings of the IEICE General Conference, 1999, 19990308
  549. A study of compact and multi-banks memory suitable for LSI, Technical report of IEICE. DSP, 102(167), 125-130, 20020620
  550. Gray-Scale/Color Image-Segmentation Architecture based on Cell-Network, Technical report of IEICE. DSP, 102(168), 49-54, 20020621
  551. Small-Area Multi-Port Register Files due to Bank Structure for Highly Parallel Processors, Technical report of IEICE. DSP, 102(169), 31-36, 20020622
  552. Comparison of the Hierarchical and Crossbar-based Architectures for the Construction Multibank Multiport Memory, Technical report of IEICE. DSP, 102(169), 37-42, 20020622
  553. A Dynamic Thernary CAM in 130nm CMOS Technology With Planar Complementary Capacitors, Technical report of IEICE. DSP, 103(380), 77-82, 20031017
  554. A study of compact and multi-banks memory suitable for LSI, Technical report of IEICE. VLD, 102(164), 125-130, 20020620
  555. Gray-Scale/Color Image-Segmentation Architecture based on Cell-Network, Technical report of IEICE. VLD, 102(165), 49-54, 20020621
  556. Small-Area Multi-Port Register Files due to Bank Structure for Highly Parallel Processors, Technical report of IEICE. VLD, 102(166), 31-36, 20020622
  557. Register Access Scheduling Logic for Superscalar Processors with Multi-Bank Register File, Technical report of IEICE. VLD, 102(684), 49-54, 20030228
  558. Evaluation of Compact Multi-bank Memory using Multi-stage Interconnection Network, Technical report of IEICE. VLD, 102(684), 55-60, 20030228
  559. A Hypergraph Partitioning Algorithm Considering Path-Cut Constraints for Circuit Partitioning, Technical report of IEICE. VLD, 96(555), 49-56, 19970306
  560. An MCM Routing Method for Via Minimization Considering Cross talk, Technical report of IEICE. VLD, 93(391), 31-38, 19931216
  561. A formal verification method based on circut partitioning corsidering BDD size, Technical report of IEICE. VLD, 93(391), 47-54, 19931216
  562. A Parallel Timing Driven Standard Cell Placement Method with Nonlinear Programming, Technical report of IEICE. VLD, 95(421), 73-78, 19951215
  563. The Processor IP for Research with Software Development Environment, Technical report of IEICE. VLD, 101(467), 121-126, 20011122
  564. A Parallel Algorithm for Graph Bisection Suitable for VLSI Implementation, The Transactions of the Institute of Electronics,Information and Communication Engineers. A, 78(6), 692-701, 19950625
  565. A Standard Cell Global Routing Algorithm with Net Selection for Over-the Cell Routing, The Transactions of the Institute of Electronics,Information and Communication Engineers. A, 77(12), 1708-1718, 19941201
  566. An Adaptive Method of Selecting Crossover Operators in a Genetic Algorithm, The Transactions of the Institute of Electronics,Information and Communication Engineers., 81(7), 900-909, 199807
  567. Register Access Scheduling Logic for Superscalar Processors with Multi-Bank Register File, Technical report of IEICE. ICD, 102(686), 49-54, 20030228
  568. A Dynamic Thernary CAM in 130nm CMOS Technology With Planar Complementary Capacitors, Technical report of IEICE. ICD, 103(382), 77-82, 20031017
  569. A Hypergraph Partitioning Algorithm Considering Path-Cut Constraints for Circuit Partitioning, Technical report of IEICE. ICD, 96(557), 49-56, 19970306
  570. Architecture for Compact and Fast Associative-Memories with All-Parallel Nearest-Match Hamming-Distance Search, Technical report of IEICE. ICD, 101(1), 27-34, 20010405
  571. The Processor IP for Research with Software Development Environment, Technical report of IEICE. ICD, 101(470), 121-126, 20011122
  572. An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints, IEICE Trans. Fundamentals, A, 83(12), 2569-2576, 20001201
  573. A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC, IEICE transactions on electronics, 89(11), 1612-1619, 20061101
  574. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, 2006(111), 39-44, 20061026
  575. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, IEICE technical report, 106(314), 39-44, 20061019
  576. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, IEICE technical report, 106(318), 39-44, 20061019
  577. Multiple CAM Matches and Self-adapting Codeword Table for Optimized Real-time Huffman Encoding, IEICE technical report, 106(425), 125-130, 20061207
  578. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, 2006(111), 39-44, 20061026
  579. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, IEICE technical report, 106(314), 39-44, 20061019
  580. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, IEICE technical report, 106(318), 39-44, 20061019
  581. Parallel Processing of Morphological Pattern Spectrum for a Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1, IEEJ Transactions on Electronics, Information and Systems, 139(3), 237-246, 2019
  582. Root growth detection with a sound wave-based simple measurement method:: Comparison verification with the visualization image of root growth, The Proceedings of the Symposium on Micro-Nano Science and Technology, 2019(0), 2019
  583. Development of growth parameter estimation method about plant micro fluidic system, The Proceedings of the Symposium on Micro-Nano Science and Technology, 2019(0), 2019
  584. Development of mobile fertilization machine with condensed liquid fertilizer, The Proceedings of the Symposium on Micro-Nano Science and Technology, 2019(0), 2019
  585. Real-time Huffman encoder with pipelined CAM-based data path and code-word-table optimizer, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 334-345, 2007
  586. A needle-type micro-sampling device for collecting nanoliter sap sample from plants, ANALYTICAL AND BIOANALYTICAL CHEMISTRY, 2021
  587. A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E104A(4), 691-701, 202104
    Link to Paper Search Results by DOI
  588. Development of multi-class computer-aided diagnostic systems using the NICE/JNET classifications for colorectal lesions, JOURNAL OF GASTROENTEROLOGY AND HEPATOLOGY, 37(1), 104-110, 202201
    Link to Paper Search Results by DOI
  589. Feasibility Study for Computer-Aided Diagnosis System with Navigation Function of Clear Region for Real-Time Endoscopic Video Image on Customizable Embedded DSP Cores, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E105A(1), 58-62, 202201
    Link to Paper Search Results by DOI
  590. Development of multi-class computer-aided diagnostic systems using the NICE/JNET classifications for colorectal lesions, JOURNAL OF GASTROENTEROLOGY AND HEPATOLOGY, 37(1), 104-110, 2022
  591. A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E104A(4), 691-701, 2021
  592. Classification with CNN features and SVM on Embedded DSP Core for Colorectal Magnified NBI Endoscopic Video Image, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E105A(1), 25-34, 2022
  593. Feasibility Study for Computer-Aided Diagnosis System with Navigation Function of Clear Region for Real-Time Endoscopic Video Image on Customizable Embedded DSP Cores, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E105A(1), 58-62, 2022
  594. Quantitative identification of mucosal gastric cancer under magnifying endoscopy with flexible spectral imaging color enhancement., Journal of gastroenterology and hepatology, 28(5), 2013
  595. Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition., Artificial intelligence in medicine, 68, 2016
  596. A needle-type micro-sampling device for collecting nanoliter sap sample from plants., Analytical and bioanalytical chemistry, 413(11), 2021
  597. Development of multi-class computer-aided diagnostic systems using the NICE/JNET classifications for colorectal lesions., Journal of gastroenterology and hepatology, 37(1), 2022
  598. Spectroscopic studies on the electronic and magnetic states of Co-doped perovskite manganite Pr0.8Ca0.2Mn1-yCoyO3 thin films, 20131112
  599. Classicalization of Quantum Variables and Quantum-Classical Hybrids, 20150623
  600. Quantum-classical hybrids in a simplified model of QED and geometric phase induced by charged particle trajectory, 20160215
  601. Memory Effect in Upper Bound of Heat Flux Induced by Quantum Fluctuations, 20161013
  602. Perturbative Expansion of Irreversible Work in Fokker-Planck Equation a la Quantum Mechanics, 20170714
  603. Nonequilibrium Work Relation from Schroedinger's Unrecognized Probability Theory, 20180117
  604. Quantum Analysis and Thermodynamic Operator Relations in Stochastic Energetics, 20170915
  605. Poisson bracket operator, 20211004
  606. Ezh2 loss propagates hypermethylation at T cell differentiation-regulating genes to promote leukemic transformation., The Journal of clinical investigation, 128(9), 2018
  607. Developing a reliable learning model for cognitive classification tasks using an associative memory, Proceedings of the 2007 IEEE Symposium on Computational Intelligence in Image and Signal Processing, CIISP 2007, 214-219, 20070925
  608. A 0.6-Tbps, 16-port SRAM design with 2-stage-pipeline and multi-stage-sensing scheme, ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference, 320-323, 20071201
  609. CAM enhanced super parallel SIMD processor with high-speed pattern matching capability, Midwest Symposium on Circuits and Systems, 803-806, 20071201
  610. Fully parallel associative memory with human memory type learning model, 2007 10th International Conference on Computer and Information Technology, ICCIT, 20071201
  611. Fully parallel single and two-stage associative memories for high speed pattern matching, Proceedings of ICECE 2008 - 5th International Conference on Electrical and Computer Engineering, 291-296, 20081201
  612. Low power and area efficient image segmentation VLSI architecture using 2-dimensional pixel-block scanning, 2008 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2008, 20090101
  613. Grouping method based on feature matching for tracking and recognition of complex objects, 2008 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2008, 20090101
  614. Associative-memory-based prototype LSI with recognition and on-line learning capability and its application to handwritten characters, ISPACS 2009 - 2009 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings, 627-630, 20091201
  615. VLSI-architecture for enabling multiple parallel associative searches with standard SRAM macros, ISPACS 2009 - 2009 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings, 45-48, 20091201
  616. A scalable massively parallel processor for real-time image processing, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 53, 334-335, 20100518
  617. Realization of efficient and low-power parallel face-detection with massive-parallel memory-embedded SIMD matrix, Midwest Symposium on Circuits and Systems, 359-362, 20100920
  618. Architecture and FPGA-implementation of scalable picture segmentation by 2D scanning with flexible pixel-block size, Proceedings - 2010 1st International Conference on Networking and Computing, ICNC 2010, 128-132, 20101201
  619. Optimization vector quantization by adaptive associative-memory- based codebook learning in combination with Huffman coding, Proceedings - 2010 1st International Conference on Networking and Computing, ICNC 2010, 15-19, 20101201
  620. Microscopic Derivation of Causal Diffusion Equation using Projection Operator Method, 20050822
  621. Chiral and Color-superconducting Phase Transitions with Vector Interaction in a Simple Model, 20021101
  622. Effects of Vector Coupling on Chiral and Color-superconducting Phase Transitions -- interplay among the scalar, pairing and vector interaction --, 20021212
  623. Pseudogap of Color Superconductivity in Heated Quark Matter, 20040919
  624. Langevin Dynamics of Chiral Phase Transition at Finite Temperature and Density, 20040709
  625. Phenomenological approach to the critical dynamics of the QCD phase transition revisited, 20050712
  626. Precursor of Color Superconductivity in Hot Quark Matter, 20020414
  627. Microscopic formula for transport coefficients of causal hydrodynamics, 20070622
  628. Solving the rectangular packing problem by an adaptive GA based on sequence-pair, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1999-January, 181-184, 19990101
  629. Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 99-104, 20001201
  630. A standard cell global routing algorithm with net selection for over‐the‐cell routing, Electronics and Communications in Japan (Part III: Fundamental Electronic Science), 78(12), 102-115, 19950101
  631. Pin assignment with global routing for VLSI building block layout, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(12), 1575-1583, 19961201
  632. A three-layer over-the-cell multi-channel router for a new cell model, Integration, the VLSI Journal, 21(3), 171-189, 19961201
  633. A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs, Integration, the VLSI Journal, 24(1), 53-77, 19970101
  634. A timing-driven floorplanning algorithm with the Elmore delay model for building block layout, Integration, the VLSI Journal, 27(1), 57-76, 19990101
  635. An iterative improvement circuit partitioning algorithm under path delay constraints, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E83-A(12), 2569-2576, 20000101
  636. An LSI implementation of an adaptive genetic algorithm with on-the-fly crossover operator selection, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1999-January, 37-40, 19990101
  637. Genetic algorithm accelerator GAA-II, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 9-10, 20001201
  638. Solving the capacitor placement problem in a radial distribution system using an adaptive genetic algorithm, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 1498 LNCS, 1028-1037, 19980101
  639. An architecture for compact associative memories with deca-ns nearest-match capability up to large distances, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 443, 170-171, 20010101
  640. Compact associative-memory architecture with fully parallel search capability for the minimum hamming distance, IEEE Journal of Solid-State Circuits, 37(2), 218-227, 20020201
  641. A Cost-efficient Dynamic Ternary CAM in 130nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 83-84, 20031001
  642. Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 252-255, 20021201
  643. Distributed against centralised crossbar function for realising bank-based multiport memories, Electronics Letters, 40(2), 101-103, 20040122
  644. Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports, Electronics Letters, 40(3), 160-162, 20040205
  645. Compact 12-port multi-bank register file test-chip in 0.35μm CMOS for highly parallel processors, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 551-552, 20040601
  646. Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 543-544, 20040601
  647. A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 47, 162-163+502, 20031201
  648. A novel hierarchical multi-port cache, European Solid-State Circuits Conference, 405-408, 20031201
  649. A nearest-Hamming-distance search memory with fully parallel mixed digital-analog match circuitry, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2003-January, 591-592, 20030101
  650. Real-time segmentation architecture of gray-scale/color motion pictures and digital test-chip implementation, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, 237-240, 20020101
  651. Optimized multi-stage minimum-distance-search circuit with feedback-stabilization for fully-parallel associative memories, Midwest Symposium on Circuits and Systems, 1, 20041201
  652. Analog-circuit-component optimization with genetic algorithm, Midwest Symposium on Circuits and Systems, 1, 20041201
  653. A hierarchical placement method for standard cell layout based on wire length driven clustering, Midwest Symposium on Circuits and Systems, 3, 20041201
  654. Low power bank-based multi-port SRAM design due to bank standby mode, Midwest Symposium on Circuits and Systems, 1, 20041201
  655. Low-power design for real-time image segmentation LSI and compact digital CMOS implementation, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 432-433, 20041201
  656. A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture, IEEE Journal of Solid-State Circuits, 40(1), 245-251, 20050101
  657. Chip size and performance evaluations of shared cache for on-chip multiprocessor, Systems and Computers in Japan, 36(9), 1-13, 20050801
  658. 350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 531-532, 20040601
  659. A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 47, 20040602
  660. A CAM-based signature-matching Co-processor with application-driven power-reduction features, IEICE Transactions on Electronics, E88-C(6), 1332-1342, 20050101
  661. Pixel-parallel digital CMOS implementation of image segmentation by region growing, IEE Proceedings: Circuits, Devices and Systems, 152(6), 579-589, 20051201
  662. Embedded low-power dynamic TCAM architecture with transparently scheduled refresh, IEICE Transactions on Electronics, E88-C(4), 622-629, 20050101
  663. Design of Superscalar processor with multi-bank register file, Proceedings - IEEE International Symposium on Circuits and Systems, 3507-3510, 20051201
  664. Superscalar processor with multi-bank register file, Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, 2005, 3-12, 20051201
  665. Multi-port CAM based VLSI architecture for huffman coding with real-time optimized code word table, Midwest Symposium on Circuits and Systems, 2005, 55-58, 20051201
  666. CAM-based VLSI architecture for huffman coding with real-time optimization of the code word table, Proceedings - IEEE International Symposium on Circuits and Systems, 5202-5205, 20051201
  667. A parallel hardware design for parametric active contour models, IEEE International Conference on Advanced Video and Signal Based Surveillance - Proceedings of AVSS 2005, 2005, 609-613, 20051201
  668. Evaluation of bank-based multiport memory architecture with blocking network, Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 89(6), 22-33, 20060601
  669. Performance evaluation of superscalar processor with multi-bank register file and an implementation result, WSEAS Transactions on Computers, 5(9), 1993-2000, 20060901
  670. Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, 176-181, 20060919
  671. An LSI hardware design for online character recognition using associative memory, Midwest Symposium on Circuits and Systems, 2005, 464-467, 20051201
  672. Multi-bank register file for increased performance of highly-parallel processors, ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference, 154-157, 20061201
  673. A learning OCR system using short/long-term memory approach and hardware implementation in FPGA, 2006 IEEE Congress on Evolutionary Computation, CEC 2006, 687-693, 20061201
  674. Multi-object tracking VLSI architecture using image-scan based region growing and feature matching, Proceedings - IEEE International Symposium on Circuits and Systems, 5575-5578, 20061201
  675. Access queues for multi-bank register files enabling enhanced performance of highly parallel processors, IEEE Region 10 Annual International Conference, Proceedings/TENCON, 20060101
  676. An FPGA-based region-growing video segmentation system with boundary-scan-only LSI architecture, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 944-947, 20061201
  677. Application of multi-ported CAM for parallel coding, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 1859-1862, 20061201
  678. Unified data/instruction cache with hierarchical multi-port architecture and hidden precharge pipeline, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 1297-1300, 20061201
  679. Fully parallel associative memory architecture with mixed digital-analog match circuit for nearest Euclidean distance search, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 1309-1312, 20061201
  680. Object tracking in video pictures based on image segmentation and pattern matching, Proceedings - IEEE International Symposium on Circuits and Systems, 3215-3218, 20051201
  681. A low-power video segmentation LSI with boundary-active-only architecture, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2, 20051201
  682. Efficient vertical/horizontal-space 1D-DCT processing based on massive-parallel matrix-processing engine, Proceedings - IEEE International Symposium on Circuits and Systems, 525-528, 20070101
  683. Low-power word-parallel nearest-hamming-distance search circuit based on frequency mapping, ESSCIRC 2010 - 36th European Solid State Circuits Conference, 538-541, 20101227
  684. A 381 fs/bit, 51.7 nW/bit nearest Hamming-distance search circuit in 65 nm CMOS, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 192-193, 20110916
  685. Real-time hybrid learning and recognition system with software-hardware cooperation, 2011 IEEE International Conference on Robotics and Biomimetics, ROBIO 2011, 2505-2510, 20111201
  686. Labeling colorectal NBI zoom-videoendoscope image sequences with MRF and SVM, Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS, 4831-4834, 20131031
  687. Power electronics education using the integrated circuit consistent education system and TCAD, Proceedings - Frontiers in Education Conference, FIE, 1456-1458, 20131201
  688. Smoothing posterior probabilities with a particle filter of dirichlet distribution for stabilizing colorectal NBI endoscopy recognition, 2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings, 621-625, 20130101
  689. Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection, Proceedings - IEEE International Symposium on Circuits and Systems, 1532-1535, 20140101
  690. FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification, Proceedings - IEEE International Symposium on Circuits and Systems, 2515-2518, 20140101
  691. Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition, Proceedings - IEEE International Symposium on Circuits and Systems, 2535-2538, 20140101
  692. SVM-MRF segmentation of colorectal NBI endoscopic images, 2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2014, 4739-4742, 20141102
  693. FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 2015-February(February), 651-654, 20150205
  694. Low cost hardware implementation for traffic sign detection system, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 2015-February(February), 363-366, 20150205
  695. Trade-off between speed and performance for colorectal endoscopic NBI image classification, Progress in Biomedical Optics and Imaging - Proceedings of SPIE, 9413, 20150101
  696. Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images, Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS, 2015-November, 2997-3000, 20151104
  697. Transfer learning for Bag-of-Visual words approach to NBI endoscopic image classification, Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS, 2015-November, 785-788, 20151104
  698. Computer-aided diagnosis of colorectal polyp histology by using a real-time image recognition system and narrow-band imaging magnifying colonoscopy, Gastrointestinal Endoscopy, 83(3), 643-649, 20160301
  699. Discriminative subtree selection for NBI endoscopic image labeling, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 10117 LNCS, 610-624, 20170101
  700. Breast tumor tissues classification using the modified cole-cole parameters with machine learning technique, IET Conference Publications, 2018(CP741), 20180101
  701. Parallel processing of morphological pattern spectrum for a massive-parallel memory-embedded SIMD matrix processor MX-1, IEEJ Transactions on Electronics, Information and Systems, 139(3), 237-246, 20190101
  702. Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM, IEEE Region 10 Annual International Conference, Proceedings/TENCON, 2018-October, 1663-1666, 20190222
  703. A hardware implementation of colorectal tumor classification for endoscopic video on customizable DSP toward real-time computer-aided diagnosis system, Proceedings - IEEE International Symposium on Circuits and Systems, 2019-May, 20190101
  704. Development of in-situ monitoring system for crop growth observation, 2019 2nd International Symposium on Devices, Circuits and Systems, ISDCS 2019 - Proceedings, 20190521
  705. Low cost and robust field-deployable environmental sensor for smart agriculture, 2019 2nd International Symposium on Devices, Circuits and Systems, ISDCS 2019 - Proceedings, 20190521
  706. An Iot-gateway with the information-centric communication, 2019 2nd International Symposium on Devices, Circuits and Systems, ISDCS 2019 - Proceedings, 20190521
  707. Nano-litter micro sampling device for extracting sample from plants, 22nd International Conference on Miniaturized Systems for Chemistry and Life Sciences, MicroTAS 2018, 4, 2273-2276, 20180101
  708. Development of a low-invasive sound-based root growth detection system, IFAC-PapersOnLine, 52(30), 225-230, 20190101
  709. Novel micro-fluidic circuit model of plant vascular system for the growth navigation, 23rd International Conference on Miniaturized Systems for Chemistry and Life Sciences, MicroTAS 2019, 92-93, 20190101
  710. Development of controlled release tablet reagents embedded compact nutrient analyzer for continuous monitoring of nutrient content in crop body, 23rd International Conference on Miniaturized Systems for Chemistry and Life Sciences, MicroTAS 2019, 1488-1489, 20190101
  711. Feature extraction of colorectal endoscopic images for computer-aided diagnosis with CNN, 2019 2nd International Symposium on Devices, Circuits and Systems, ISDCS 2019 - Proceedings, 20190521
  712. Dragonfly-Like Micro Sampling Device for Extracting Nano-Liter Sample from Plants, 2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems and Eurosensors XXXIII, TRANSDUCERS 2019 and EUROSENSORS XXXIII, 697-700, 20190601
  713. Multistep reactions by aligned tablet reagents for long term monitoring of plant culture solution, MicroTAS 2020 - 24th International Conference on Miniaturized Systems for Chemistry and Life Sciences, 478-479, 20200101
  714. Classification Method with CNN features and SVM for Computer-Aided Diagnosis System in Colorectal Magnified NBI Endoscopy, IEEE Region 10 Annual International Conference, Proceedings/TENCON, 2020-November, 1095-1100, 20201116
  715. A hardware implementation on customizable embedded dsp core for colorectal tumor classification with endoscopic video toward real-time computer-aided diagnosais system, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E104.A(4), 691-701, 20210401
  716. A Lesion Classification Method Using Deep Learning Based on JNET Classification for Computer-Aided Diagnosis System in Colorectal Magnified NBI Endoscopy, 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021, 20210627
  717. Sweat Droplets Detection Using Deep Learning for the Impression Mold Technique to Evaluate Sweating Responses to Thermal Stimulus, 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021, 20210627
  718. Automatic Detection of Skin Surface Structure Using Deep Learning for the Impression Mold Technique, 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021, 20210627
  719. A Lesion Classification Method Using Deep Learning Based on NICE Classification for Computer-Aided Diagnosis System in Colorectal NBI Endoscopy, 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021, 20210627
  720. An Image Segmentation Method for Automatic Analysis of Skin Surface Structure in Atopic Dermatitis by the Impression Mold Technique, Midwest Symposium on Circuits and Systems, 2021-August, 563-566, 20210809
  721. Sweat Droplets Detection Using Image Segmentation on Skin Surface for Evaluation of Sweating Responses to Thermal Stimulus in Atopic Dermatitis, Midwest Symposium on Circuits and Systems, 2021-August, 559-562, 20210809
  722. AN OPTIMAL CHANNEL PIN ASSIGNMENT ALGORITHM FOR HIERARCHICAL BUILDING-BLOCK LAYOUT DESIGN, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E76A(10), 1636-1644, 1993
  723. A GRAPH BISECTION ALGORITHM-BASED ON SUBGRAPH MIGRATION, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E77A(12), 2039-2044, 1994
  724. A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs, INTEGRATION-THE VLSI JOURNAL, 24(1), 53-77, 1997
  725. Solving the capacitor placement problem in a radial distribution system using an adaptive genetic algorithm, PARALLEL PROBLEM SOLVING FROM NATURE - PPSN V, 1498, 1028-1037, 1998
  726. An iterative improvement circuit partitioning algorithm under path delay constraints, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E83A(12), 2569-2576, 2000
  727. A FLOORPLANNING METHOD WITH TOPOLOGICAL CONSTRAINT MANIPULATION IN VLSI BUILDING-BLOCK LAYOUT, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E77A(12), 2053-2057, 1994
  728. A standard cell global routing algorithm with net selection for over-the-cell routing, ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 78(12), 102-115, 1995
  729. A three-layer over-the-cell multi-channel router for a new cell model, INTEGRATION-THE VLSI JOURNAL, 21(3), 171-189, 1996
  730. Pin assignment with global routing for VLSI building block layout, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 15(12), 1575-1583, 1996
  731. An efficient timing-driven global routing method for standard cell layout, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E79D(10), 1410-1418, 1996
  732. Mixed planar and H-V over-the-cell routing for standard cells with nonuniform over-the-cell routing capacities, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E79D(10), 1419-1430, 1996
  733. Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 37(2), 218-227, 2002
  734. A performance-driven floorplanning method with interconnect performance estimation, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A(12), 2775-2784, 2002
  735. Efficient video-picture segmentation algorithm for cell-network-based digital CMOS implementation, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E87D(2), 500-503, 2004
  736. A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 40(1), 245-253, 2005
  737. Boundary-active-only adaptive power-reduction scheme for region-growing video-segmentation, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E89D(3), 1299-1302, 2006
  738. Memory Effect and Fast Spinodal Decomposition, 20070828
  739. Shock propagation and stability in causal dissipative hydrodynamics, 20080512
  740. Stability and Causality in relativistic dissipative hydrodynamics, 20080719
  741. Extensivity of Irreversible Current and Stability in Causal Dissipative Hydrodynamics, 20090126
  742. Shear viscosity coefficient and relaxation time of causal dissipative hydrodynamics in QCD, 20090630
  743. A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E81A(12), 2476-2484, 1998
  744. Effect of bulk viscosity on Elliptic Flow near QCD phase transition, 20091010
  745. Extended Thermodynamic Relation and Fluctuation Theorem in Stochastic Dynamics with Time Reversed Process, 20090720
  746. Bulk viscosity effects on elliptic flow, 20090930
  747. The effect of shear and bulk viscosities on elliptic flow, 20100211
  748. Dissipative relativistic fluid dynamics: a new way to derive the equations of motion from kinetic theory, 20100428
  749. Schroedinger Equation in Rotating Frame by using Stochastic Variational Method, 20161122
  750. More quantum centrifugal effect in rotating frame, 20170505
  751. Uncertainty relation for angle from a quantum-hydrodynamical perspective, 20200316
  752. Dynamical Correlations as Origin of Nonextensive Entropy, 20050616
  753. How Far Can the SO(10) Two Higgs Model Describe the Observed Neutrino Masses and Mixings ?, 20020223
  754. Incorporating Memory Effects in Phase Separation Processes, 20060315
  755. Open Problems in Hydrodynamical Approach to Relativistic Heavy Ion Collisions, 20060614
  756. Relativistic Dissipative Hydrodynamics: A Minimal Causal Theory, 20070322
  757. New Formulation of Causal Dissipative Hydrodynamics: Shock wave propagation, 20070119
  758. Decay process accelerated by tunneling in its very early stage, 20021025
  759. A timing-driven floorplanning algorithm with the Elmore delay model for building block layout, INTEGRATION-THE VLSI JOURNAL, 27(1), 57-76, 1999
  760. Distributed against centralised crossbar function for realising bank-based multiport memories, ELECTRONICS LETTERS, 40(2), 101-103, 2004
  761. Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports, ELECTRONICS LETTERS, 40(3), 160-162, 2004
  762. Embedded low-power dynamic TCAM architecture with transparently scheduled refresh, IEICE TRANSACTIONS ON ELECTRONICS, E88C(4), 622-629, 2005
  763. A CAM-based signature-matching co-processor with application-driven power-reduction features, IEICE TRANSACTIONS ON ELECTRONICS, E88C(6), 1332-1342, 2005
  764. Pixel-parallel digital CMOS implementation of image segmentation by region growing, IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 152(6), 579-589, 2005
  765. Evaluation of bank-based multiport memory architecture with blocking network, ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 89(6), 22-33, 2006
  766. Computer-aided diagnosis of colorectal polyp histology by using a real-time image recognition system and narrow-band imaging magnifying colonoscopy, GASTROINTESTINAL ENDOSCOPY, 83(3), 643-649, 2016
  767. Development of multi-class computer-aided diagnostic systems using the NICE/JNET classifications for colorectal lesions, Journal of Gastroenterology and Hepatology (Australia), 37(1), 104-110, 20220101
  768. Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual, Systems and Computers in Japan, 32(1), 29-37, 20010101
  769. A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time, Systems and Computers in Japan, 33(12), 87-96, 20021115

Publications such as books

  1. 2022/02/22, AgriBio, In order to understand how the environment around the crop and the application of fertilizer to the crop affect the changes in crop traits, we have developed a technique and instrumentation to acquire time-series image information of the crop and extract parameters related to the trait changes from them. This enables us to obtain information on trait changes in each part of the crop, to examine the relationship with fertilizer application and environmental conditions, and to identify quantifiable parameters. We also developed the basic technology to automatically extract and track the quantitative values of the parameters representing the trait changes from various images, such as visual and thermographic images., In order to understand how the environment around the crop and the application of fertilizer to the crop affect the changes in crop traits, we have developed a technique and instrumentation to acquire time-series image information of the crop and extract parameters related to the trait changes from them. This enables us to obtain information on trait changes in each part of the crop, to examine the relationship with fertilizer application and environmental conditions, and to identify quantifiable parameters. We also developed the basic technology to automatically extract and track the quantitative values of the parameters representing the trait changes from various images, such as visual and thermographic images., Development of image processing technology and sensors for understanding the growth status of crops, Crop growth monitoring, image processing technology, sensors, AI, Hokuryukan & NEW SCIENCE co., ltd, 2022, 2022, Scholarly Book, Contributor, 日本語, Tetsushi Koide, 01327-03, 98, 13-17
    Amazon URL
  2. 2021/11/30, Biomedical Engineering, Chapter 16, A Hierarchical Type Segmentation Hardware for Colorectal Endoscopic Images with Narrow Band Imaging Magnification, A Hierarchical Type Segmentation Hardware for Colorectal Endoscopic Images with Narrow Band Imaging Magnification, A Hierarchical Type Segmentation Hardware for Colorectal Endoscopic Images with Narrow Band Imaging Magnification, A Hierarchical Type Segmentation Hardware for Colorectal Endoscopic Images with Narrow Band Imaging Magnification, Biomedical Engineering, AI, Image Processing, VLSI, Hardware, Jenny Stanford Publishing Pte Ltd., 2021, 2021, Scholarly Book, Contributor, English, Tetsushi Koide, Toru Tamaki, Shigeto Yoshida, Shinji Tanaka, 978-9814877633, 380, 319-329
    Amazon URLAmazon Image Link (Small)

Invited Lecture, Oral Presentation, Poster Presentation

  1. An FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images, T. Okamoto, T. Koide, A. T. Hoang, T. Shimizu, K. Sugi, H. Sakurai, T. Tamaki, T. Hirakawa, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, T. Okamoto, T. Koide, A. T. Hoang, T. Shimizu, K. Sugi, H. Sakurai, T. Tamaki, T. Hirakawa, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, the 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016/10/24, Without Invitation, English
  2. Prototype Speed Limit Sign Recognition System Implementation on Rapid Prototyping Platform, A. T. Hoang, T. Okamoto, T. Koide, A. T. Hoang, T. Okamoto, T. Koide, The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016/10/24, Without Invitation, English
  3. A Hardware Accelerator for Bag-of Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2016), 2016/07/10, Without Invitation, English
  4. Compact and High-Speed Hardware Feature Extraction Accelerator for Dense Scale-Invariant Feature Transform, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2016), 2016/07/10, Without Invitation, English
  5. Visual-Word Based Feature Transformation System in Computer Aided Diagnosis for Colorectal Endoscopic Images, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, IEICE ICD, 2016/03/02, Without Invitation, Japanese, IEICE ICD, Higashi-Hiroshima
  6. A Visual-Word Based Feature Transformation System in Computer Aided Diagnosis for Colorectal Endoscopic Images, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, IEICE ICD, 2016/03/02, Without Invitation, Japanese, IEICE ICD, Higashi-Hiroshima
  7. A Type Identification System Based on Support Vector Machine in Computer Aided Diagnosis for Colorectal Endoscopic Images, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, IEICE ICD, 2016/03/02, Without Invitation, Japanese, IEICE ICD, Higashi-Hiroshima
  8. Architecture of Bottom-up Feature Construction for Robust Computer-Aided Diagnosis System, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, 2015/12/01, Without Invitation, Japanese, Nagasaki
  9. Suitable Feature Extraction Architecture for Real-time Computer Aided Diagnosis System on Gastrointestinal Tract, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, 2015/12/01, Without Invitation, Japanese, IEICE RECONF, Nagasaki
  10. Probability Estimation Hardware on SVM for Type Identification of Colorectal Endoscopic Images, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, 2015/12/01, Without Invitation, Japanese
  11. An Implementation of Speed Limit Traffic Sign Recognition System on Rapid Prototyping Platform, H. Sato, T. Koide, A. Hoang, T. Okamoto, H. Sato, T. Koide, A. Hoang, T. Okamoto, 2015/12/01, Without Invitation, Japanese, Nagasaki

Awards

  1. 2022/07/06, The 36thInternational Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2021), Best Paper Award, President of IEIE, Automatic Detection of Skin Surface Structure Using Deep Learning for the Impression Mold Technique
  2. 2016/10/24, Outstanding Paper Award SASIMI2016, General Chair Technical Program Committee Chair
  3. 2003/01, "Asia and South Pachific Design Automation Conference 2003University LSI Design Contest, Special Feature Award", ASP-DAC2003 Univ. LSI Design Contest Com, A Nearest-Hamming-Distance Search Memory With Fully Parallel Mixed Digital-Analog Match Circuitry
  4. 2018/11/10, Young Researchers Poster Award, General Chair, The 2nd International Symposium on Biomedical Engineering, A Hardware Accelerator for Bag-of-Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images
  5. 2017/12/13, The 19th IEEE Hiroshima Branch Student Symposium (HISS) Excellence Research Award, IEEE Hiroshima Chapter, Identification method using CNN features and SVM classification for colonoscopic image real time diagnosis support system

Patented

  1. Patent, 10062161, 2018/08/28
  2. Patent, 3095376, 2018/06/27
  3. Patent, 6355908, 2018/06/22
  4. Patent, 9959473, 2018/05/01

External Funds

Acceptance Results of Competitive Funds

  1. 2021
  2. KAKENHI(Grant-in-Aid for Scientific Research (B)), 2017, 2019
  3. KAKENHI, 2016, 2018
  4. Strategic Basic Research Programs(CREST), 2015/12/01, 2018/03/31
  5. Strategic Basic Research Programs(CREST), 2015/12/01, 2019/03/31
  6. Strategic Basic Research Programs(CREST), 2015/12/01, 2020/03/31
  7. KAKENHI, 2014, 2016
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  8. Adaptable and Seamless Technology transfer Program through targetdriven R&D, 2013/08/01, 2014/03/31
  9. KAKENHI, 2012, 2014
    Permalink
  10. KAKENHI, Study on a functional memory-based VLSI system to grow and adapt to the environment, 2011, 2013
    Permalink
  11. KAKENHI, Electromagnetic wave propagation for cancer detection, 2009, 2012
    Permalink
  12. KAKENHI, Memory-based VLSI brain research for realizing recognition, learning and decision capability, 2007, 2009
    Permalink
  13. KAKENHI, 2004, 2005
    Permalink
  14. KAKENHI, A 3 Dimensional Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains, 2003, 2007
    Permalink
  15. KAKENHI, A Study on Automatic Layout Design System for Deep-Submicron High-Performance VLSI, 2000, 2001
    Permalink
  16. KAKENHI, 2000, 2001
    Permalink
  17. KAKENHI, A Study on Processor Architecture Dedicated for Adaptive Genetic Algorithms, 2000, 2001
    Permalink
  18. KAKENHI, Fast and small area associative memories with minimum distance search capability, 2000, 2001
    Permalink
  19. KAKENHI, A Study on Hardware Implementation of a Genetic Algorithm with Adaptive Parameter Adjustment, 1998, 1999
    Permalink
  20. KAKENHI, 1998, 1999
    Permalink
  21. KAKENHI, 1996, 1996
    Permalink
  22. KAKENHI, 1994, 1994
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  23. KAKENHI, 1994, 1994
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  24. KAKENHI, A study on VLSI layout methods based on meta-heuristics, 1993, 1994
    Permalink
  25. KAKENHI, A method for constructing a reliable distributed network system for on-line transaction processing, 1992, 1993
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  26. Strategic Basic Research Programs(CREST), 2015/12/01, 2021/03/31
  27. Strategic Basic Research Programs(CREST), 2015/12/01, 2021/03/31
  28. Strategic Basic Research Programs(CREST), 2015/12/01, 2021/03/31
  29. KAKENHI(Grant-in-Aid for Scientific Research (B)), 2020, 2022

Social Activities

History as Committee Members

  1. TPC Vice Chair of International Conference on Solid State Devices and Materials, 2012, International Conference on Solid State Devices and Materials
  2. TPC Vice Chair of International Conference on Solid State Devices and Materials, 2011, International Conference on Solid State Devices and Materials
  3. TPC Vice Chair of International Conference on Solid State Devices and Materials, 2010, International Conference on Solid State Devices and Materials

Organizing Academic Conferences, etc.

  1. International Symposium on Devices, Circuits and Systems (ISDCS), Technical Program Char, 2019/06, 2019/06
  2. The 3rd Interational Symposium on Biomedical Engineering (ISBE2018), Organizing Committee, 2018/11, 2018/11
  3. International Workshop on Nanodevice Technologies 2018, Organizing Committee, 2018/03, 2018/03
  4. The 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2018), Technical Program Committee, 2018/03, 2018/03
  5. International Workshop on Nanodevice Technologies 2017, Organizing Committee, 2017/03, 2017/03
  6. International Workshop on Nanodevice Technologies 2015, Organizing Committee, 2015/03, 2015/03
  7. International Workshop on Nanodevice Technologies 2013, Organizing Committee, 2013/03, 2013/03
  8. 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013), Organizing Committee, 2013/01, 2013/01
  9. International Conference on Solid State Devices and Materials (SSDM2011), Technical Program Committee Vice Chair (Area 5. Advanced Circuits and System), 2011/09, 2011/09
  10. 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Organizing Committee, 2011/01, 2011/01
  11. International Conference on Solid State Devices and Materials (SSDM2010), Technical Program Committee Vice Chair (Area 5. Advanced Circuits and System), 2010/09, 2010/09