Tetsushi Koide

Last Updated :2021/04/18

Affiliations, Positions
Research Institute for Nanodevice and Bio Systems, Associate Professor
Web Site
E-mail
koidecomputer.orgkoidehiroshima-u.ac.jp
Other Contact Details
"1-4-2, KAGAMIYAMA, HIGASHI-HIROSHIMA, HIROSHIMA, 739-8527, JAPAN", Japan
TEL : (+81)824-24-6265 FAX : (+81)824-24-3499
Self-introduction
I am conducting research on medical image (cancer) diagnosis support (CAD) systems, artificial intelligence information integration (LSI) systems, and agricultural support systems using IoT. If you would like to know about my research project, please search "Tetsushi Koide Hiroshima University" in Google Search Engine

Basic Information

Major Professional Backgrounds

  • 2001/05/01, The University of Tokyo, VLSI Design and Education Center (VDEC), Visiting Researcher
  • 2004/04/01, Hiroshima University, Department of Semiconductor Electronics and Integration Sciences, Associate Professor
  • 2000/04/01, 2001/03/31, Hiroshima University, Faculty of Engineering, Visiting Associate Professor
  • 1999/04/01, 2000/03/31, Hiroshima University, Faculty of Engineering, Associate Professor
  • 1999/03/01, 1999/03/31, Hiroshima University, Faculty of Engineering, Associate Professor
  • 1992/04/01, 1999/02/28, Hiroshima University, the Faculty of Engineering, Research Associate
  • 1996/04/01, 1996/10/09, Yuge National College of Maritime Technology, Visiting Assistant Professor
  • 2001/04/01, Hiroshima University, Research Center for Nanodevices and Systems, Associate Professor
  • 1999/04/01, 2001/03/31, The University of Tokyo, VLSI Design and Education Center (VDEC), Associate Professor

Educational Backgrounds

  • Hiroshima University, Graduate School, Division of Engineering, System Engineering, Japan, 1990/04, 1992/03
  • Hiroshima University, Faculty of Engineering, Japan, 1986/04, 1990/03

Academic Degrees

  • Doctor Engineering, Hiroshima University
  • Master of Engineering, Hiroshima University

Educational Activity

  • 【Master's Program】Graduate School of Advanced Science and Engineering : Division of Advanced Science and Engineering : Quantum Matter Program
  • 【Doctoral Program】Graduate School of Advanced Science and Engineering : Division of Advanced Science and Engineering : Quantum Matter Program

In Charge of Primary Major Programs

  • Program of Electrical,Systems and Information Engineering
  • Electrical, Computer, and Systems Engineering
  • Electronic Devices and Systems

Research Fields

  • Informatics;Computing Technologies;Computer system
  • Informatics;Computing Technologies;High performance computing
  • Informatics;Human informatics;Perceptual information processing
  • Informatics;Human informatics;Intelligent informatics
  • Complex systems;Biomedical engineering;Medical systems
  • Complex systems;Biomedical engineering;Biomedical engineering / Biomaterial science and engineering
  • Engineering;Electrical and electronic engineering;Electron device / Electronic equipment
  • Engineering;Electrical and electronic engineering;Electronic materials / Electric materials
  • Engineering;Electrical and electronic engineering;Control engineering / System engineering
  • Agricultural sciences;Agroengineering;Agricultural environmental engineering / Agriculturalinformation engineering
  • Informatics;Frontiers of informatics;Life / Health / Medical informatics

Research Keywords

  • Design Automation|Cache
  • Real Time Processing|LSI
  • LSI|Image Compression
  • Registor File|Image Segmentation
  • Digital and Analog Circuits|VLSI
  • Vector Quantaization|Image Segmentation
  • LSI|Associative Memory
  • CAD|Multi-Port Memory
  • LSI|Associative Memory
  • Learning|Motion Estimation

Affiliated Academic Societies

  • Asia and South Pacific Design Automation Conference(ASPDAC'00), 2000
  • Asia and South Pacific Design Automation Conference(ASPDAC'01), 2001
  • Asia and South Pacific Design Automation Conference(ASPDAC'02)
  • Asia and South Pacific Design Automation Conference(ASPDAC'03)
  • Asia and South Pacific Design Automation Conference(ASPDAC'04)
  • Asia and South Pacific Design Automation Conference(ASPDAC'05), 2004, 2005
  • Asia and South Pacific Design Automation Conference(ASPDAC'97), 1996
  • Asia and South Pacific Design Automation Conference(ASPDAC'98), 1997
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'00), 2000
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'01), 2001
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'03)
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'04)
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'06)
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), 1997
  • Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'98), 1998
  • IPSJ, 1994
  • IEICE, 1996, 2001
  • IEEE
  • ACM

Educational Activity

Course in Charge

  1. 2021, Undergraduate Education, 1Term, Research Tutorial IIB
  2. 2021, Undergraduate Education, 1Term, Experiments in Electrical Engineering Electronics and System Engineering I
  3. 2021, Undergraduate Education, 2Term, Experiments in Electrical Engineering Electronics and System Engineering I
  4. 2021, Undergraduate Education, 3Term, Experiments in Electrical Engineering Electronics and System Engineering II
  5. 2021, Undergraduate Education, 4Term, Experiments in Electrical Engineering Electronics and System Engineering II
  6. 2021, Undergraduate Education, 1Term, Basic Experiments in Electrical Engineering I
  7. 2021, Undergraduate Education, 2Term, Basic Experiments in Electrical Engineering I
  8. 2021, Undergraduate Education, 3Term, Basic Experiments in Electrical Engineering II
  9. 2021, Undergraduate Education, 4Term, Basic Experiments in Electrical Engineering II
  10. 2021, Undergraduate Education, 2Term, CMOS Logic Circuit Design
  11. 2021, Graduate Education (Master's Program) , First Semester, Seminar on Electronics A
  12. 2021, Graduate Education (Master's Program) , Second Semester, Seminar on Electronics B
  13. 2021, Graduate Education (Master's Program) , Academic Year, Academic Presentation in Electronics
  14. 2021, Graduate Education (Master's Program) , 1Term, Exercises in Electronics A
  15. 2021, Graduate Education (Master's Program) , 2Term, Exercises in Electronics A
  16. 2021, Graduate Education (Master's Program) , 3Term, Exercises in Electronics B
  17. 2021, Graduate Education (Master's Program) , 4Term, Exercises in Electronics B
  18. 2021, Graduate Education (Master's Program) , Academic Year, Advanced Study in Quantum Matter
  19. 2021, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Quantum Matter

Research Activities

Academic Papers

  1. Secure data processing with massive-parallel SIMD matrix for embedded SoC in digital-convergence mobile devices, IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, 12(1), 96-104, 201701
  2. Development of a Real-time Colorectal Tumor Classification System for Narrow-band Imaging zoom-video endoscopy, Cornel University Library, CoRR, 9 pages, https://arxiv.org/abs/1612.05000v2., 2017
  3. Discriminative Subtree Selection for NBI Endoscopic Image Labeling, Proceedings of the International Workshop on Nanodevice Technologies 2017, pp. 82-83, Hiroshima, Japan, March 2, 2017., 20170302
  4. A Real-Time Visual Word Feature Transformation for Colorectal Endoscopic Images with NBI Magnification, Proceedings of the International Workshop on Nanodevice Technologies 2017, pp. 84-85, March 2, 2017., 20170302
  5. A Real-Time Type Identification based on Support Vector Machine for Colorectal Endoscopic Images with NBI Magnification, Proceedings of the International Workshop on Nanodevice Technologies 2017, pp. 86-87, March 2, 2017., 20170302
  6. Discriminative Subtree Selection for NBI Endoscopic Image Labeling, Proc. of International Symposium on Biomedical Engineering, pp.170-171, Nov. 10-11, 2016., 20170302
  7. Secure data processing with massive-parallel SIMD matrix for embedded SoC in digital-convergence mobile devices, IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, 12(1), 96-104, 2017
  8. Computer-aided diagnosis of colorectal polyp histology by using a real-time image recognition system and narrow-band imaging magnifying colonoscopy, GASTROINTESTINAL ENDOSCOPY, 83(3), 643-649, 201603
  9. Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition, ARTIFICIAL INTELLIGENCE IN MEDICINE, 68, 1-16, 201603
  10. Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition, PSYCHOLOGISCHE RUNDSCHAU, 68(1), 1-16, 201603
  11. Transfer Learning for Endoscopic Image Classification, Proc. of Korea-Japan joint Workshop on Frontiers of Computer Vision (FCV2016), 1, 258-262, 2016
  12. Computer-Aided Colorectal Tumor Classification in NBI Endoscopy Using CNN Features, Proc. of Korea-Japan joint Workshop on Frontiers of Computer Vision (FCV2016), 61-65, 2016
  13. An FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images, Proc. of The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 20161024
  14. Prototype Speed Limit Sign Recognition System Implementation on Rapid Prototyping Platform, Proc. of The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016
  15. Compact and High-Speed Hardware Feature Extraction Accelerator for Dense Scale-Invariant Feature Transform, Proc. of the 31th International Technical Conference on Circuits/Systems, Computers and Communications, 20160710
  16. A Hardware Accelerator for Bag-of Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images, Proc. of the 31th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2016), 20160710
  17. Discriminative subtree selection for NBI endoscopic image labeling, Proc. of The ACCV2016 workshop on mathematical and computational methods in biomedical imaging and image analysis (MCBMIIA2016), 20161124
  18. A Real-Time Feature Extraction Method for Colorectal Endoscopic Images toward Computer-Aided Diagnosis, Proc. of International Symposium on Biomedical Engineering, pp.162-163, Nov. 10-11, 2016., 20161110
  19. A Real-Time Feature Transformation Method for Colorectal Endoscopic Images toward Computer-Aided Diagnosis, Proc. of International Symposium on Biomedical Engineering, pp.164-165, Nov. 10-11, 2016., 20161110
  20. A Real-Time Type Identification Method for Colorectal Endoscopic Images toward Computer-Aided Diagnosis, Proc. of International Symposium on Biomedical Engineering, pp.166-167, Nov. 10-11, 2016., 20161110
  21. An FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images, Proc. of The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, pp. 81-86, Oct. 24-25, 2016, 20161110
  22. Compact and High-Speed Hardware Feature Extraction Accelerator for Dense Scale-Invariant Feature Transform, Proc. of the 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2016), pp.596-599 , July 10-13, 2016, 20161110
  23. A Hardware Accelerator for Bag-of Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images, Proc. of the 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2016), pp.596-599 , July 10-13, 2016, 20160710
  24. Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition, ARTIFICIAL INTELLIGENCE IN MEDICINE, 68, 1-16, 2016
  25. "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" (vol 68, pg 1, 2016), ARTIFICIAL INTELLIGENCE IN MEDICINE, 72, 83-83, 2016
  26. Simple Yet Effective Two-Stage Speed Traffic Sign Recognition for Robust Vehicle Environments, The 30th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2015), 1, 420-423, 2015
  27. A Computer System To Be Used With Laser-based Endoscopy for Quantitative Diagnosis of Early Gastric Cancer, JOURNAL OF CLINICAL GASTROENTEROLOGY, 49(2), 108-115, 201502
  28. Real-time Speed Limit Traffic Sign Detection System for Robust Automotive Environments, IEIE Transactions on Smart Processing and Computing, 4(5), 237-250, 2015
  29. Trade-off between speed and performance for colorectal endoscopic NBI image classification, Proc. SPIE 9413, Medical Imaging 2015, 94132D, 2015
  30. High Accuracy and Simple Real-Time Circle Detection on Low-Cost FPGA for Traffic-Sign Recognition on Advanced Driver Assistance System, roceeding of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), 1, 397-402, 2015
  31. Speed Traffic-Sign Number Recognition on Low Cost FPGA for Robust Sign Distortion and Illumination Conditions, Proceeding of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), 1, 421-426, 2015
  32. High Performance Feature Transformation Architecture based on Bag-of-Features in CAD system Colorectal Endoscopic Images, Proceeding of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), 1, 380-385, 2015
  33. Effective Diagnostic Image Segmentation with Pyramid Style Support Vector Machine for Colorectal Endoscopic Images, The 30th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2015), 1, 596-599, 2015
  34. Image Segmentation of Pyramid Style Identifier based on Support Vector Machine for Colorectal Endoscopic Images, The 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC2015), 2997-3000, 2015
  35. Transfer Learning for Bag-of-Visual Words Approach to NBI endoscopic image classification, Proc. of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC2015), 785-788, 2015
  36. Trade-off between speed and performance for colorectal endoscopic NBI image classification, Proc. of SPIE Medical Imaging 2015, 9413-9416, 2015
  37. A Computer System To Be Used With Laser-based Endoscopy for Quantitative Diagnosis of Early Gastric Cancer, JOURNAL OF CLINICAL GASTROENTEROLOGY, 49(2), 108-115, 2015
  38. Quantitative identification of mucosal gastric cancer under magnifying endoscopy with flexible spectral imaging color enhancement, JOURNAL OF GASTROENTEROLOGY AND HEPATOLOGY, 28(5), 841-847, 201305
  39. Quantitative identification of mucosal gastric cancer under magnifying endoscopy with flexible spectral imaging color enhancement, JOURNAL OF GASTROENTEROLOGY AND HEPATOLOGY, 28(5), 841-847, 2013
  40. Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 47(6), 1448-1459, 201206
  41. Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal-Oxide-Semiconductor Technology Including Its Distance Dependences, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 201204
  42. High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 201204
  43. A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E95D(9), 2327-2338, 201209
  44. Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal-Oxide-Semiconductor Technology Including Its Distance Dependences, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 2012
  45. High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme, JAPANESE JOURNAL OF APPLIED PHYSICS, 51(4), 2012
  46. Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 47(6), 1448-1459, 2012
  47. A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E95D(9), 2327-2338, 2012
  48. An associative memory-based learning model with an efficient hardware implementation in FPGA, EXPERT SYSTEMS WITH APPLICATIONS, 38(4), 3499-3513, 201104
  49. Analysis of Within-Die Complementary Metal-Oxide-Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM, JAPANESE JOURNAL OF APPLIED PHYSICS, 50(4), 201104
  50. Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E94D(9), 1742-1754, 201109
  51. A Scalable Massively Parallel Processor for Real-Time Image Processing, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 46(10), 2363-2373, 201110
  52. An associative memory-based learning model with an efficient hardware implementation in FPGA, EXPERT SYSTEMS WITH APPLICATIONS, 38(4), 3499-3513, 2011
  53. Analysis of Within-Die Complementary Metal-Oxide-Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM, JAPANESE JOURNAL OF APPLIED PHYSICS, 50(4), 2011
  54. Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E94D(9), 1742-1754, 2011
  55. A Scalable Massively Parallel Processor for Real-Time Image Processing, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 46(10), 2363-2373, 2011
  56. Measurement-Based Ring Oscillator Variation Analysis, IEEE DESIGN & TEST OF COMPUTERS, 27(5), 6-13, 2010
  57. Measurement-Based Ring Oscillator Variation Analysis, IEEE DESIGN & TEST OF COMPUTERS, 27(5), 6-13, 2010
  58. Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model, IEEE ELECTRON DEVICE LETTERS, 30(8), 873-875, 200908
  59. Correlating Microscopic and Macroscopic Variation with Surface-Potential Compact Model, IEEE Electron Device Letters, 30(8), 873-875, 20090801
  60. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, Jpn. J. Appl. Phys., 48(4), 04C078, 20090401
  61. Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model, 20090601
  62. VLSI Design of a Handwritten-Character Learning and Recognition system based on Associative Memory, 161-166, 20090327
  63. Analysis of Process Variations in 90-nm CMOS Technology with Ring Oscillators, 446-449, 20090327
  64. Improved Region-Growing Image-Segmentation Algorithm Based on HSV Color Space, 167-171, 20090328
  65. A Ternary Multi-Ported Content Addressable Memory Architecture utilizing Asynchronous Multiple Search-Operation Technology, 224-229, 20090328
  66. Low Power and Area Efficient Image Segmentation VLSI Architecture Using 2-Dimensional Pixel-Block Scanning, 441-444, 20090228
  67. Grouping Method based on Feature Matching for Tracking and Recognition of Complex Objects, 421-424, 20090228
  68. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(4), 200904
  69. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, JAPANESE JOURNAL OF APPLIED PHYSICS, 48(4), 2009
  70. Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model, IEEE ELECTRON DEVICE LETTERS, 30(8), 873-875, 2009
  71. Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor, IEICE Trans. on Electronics, E91-C(9), 1409-1418, 20080901
  72. Low-Power Image-Segmentation VLSI Design Based on a Pixel-Block Scanning Architecture, 474-475, 20081008
  73. Integration architecture of content addressable memory and massive-parallel memory-embedded SIMD matrix for versatile multimedia processor, IEICE TRANSACTIONS ON ELECTRONICS, E91C(9), 1409-1418, 200809
  74. Integration architecture of content addressable memory and massive-parallel memory-embedded SIMD matrix for versatile multimedia processor, IEICE TRANSACTIONS ON ELECTRONICS, E91C(9), 1409-1418, 2008
  75. 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words, IEICE Trans. on Electronics, E90-C(11), 2157-2160, 20071101
  76. Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor, IEICE Trans. on Information & Systems, E90-D(8), 1312-1215, 20070801
  77. Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories, IEICE Trans. on Fundamentals, E90-A(6), 1240-1243, 20070601
  78. Mixed Digital-Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search, Jpn. J. Appl. Phys., 46(4B), 2231-2237, 20070401
  79. A 2-stage-pipelined 16 Port SRAM with 590 Gbps Random Access Bandwidth and Large Noise Margin, IEICE Electronics Express, 4(2), 21-25, 20070116
  80. Scalable FPGA/ASIC Implementation Architecture for Parallel Table-lookup Coding Using Multi-ported Content Addressable Memory, IEICE Trans. on Information & Systems, E90-D(1), 346-354, 20070101
  81. Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer, IEICE Trans. on Information & Systems, E90-D(1), 334-345, 20070101
  82. Static-Noise-Margin Analysis of Major SRAM-Cell Type under Production Variation for a 90nm CMOS Process, 261-265, 20071017
  83. Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories, 32-37, 20071015
  84. An Effective Parallel Coding Architecture Utilizing Characteristics of Multimedia Application, 74-80, 20071015
  85. Area Efficieant Fully Parallel Associative Memory with Fast Winner Search Capability, 38-41, 20071016
  86. Acceleration of Advanced Encryption Standard (AES) Processing on a CAM Enhanced Super Parallel SIMD Processor, 26-31, 20071016
  87. Associative Memory Design Realizing Reference-Pattern Recognition and Learning based on Short/Long-Term Storage Concept, 21-25, 20071016
  88. Performance Evaluation of Region-Growing Image Segmentation Using Two-Dimensional Image-Block Scanning, 69-73, 20071016
  89. A 0.6-Tbps, 16-Port SRAM Design with 2-Stage-Pipeline and Multi-Stage-Sensing Scheme, 320-323, 20070912
  90. CAM Enhanced Super Parallel SIMD Processor with High-Speed Pattern Matching Capability, 803-806, 20070824
  91. Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine, 525-528, 20070501
  92. Developing a Reliable Learning Model for Cognitive Classification Tasks Using an Associative Memory, 214-219, 20070401
  93. Mixed digital-analog associative memory enabling fully-parallel nearest Euclidean distance search, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(4B), 2231-2237, 200704
  94. Real-time Huffman encoder with pipelined CAM-based data path and code-word-table optimizer, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 334-345, 200701
  95. Scalable FPGA/ASIC implementation architecture for parallel table-lookup-coding using multi-ported content addressable memory, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 346-354, 200701
  96. A 2-stage-pipelined 16 port SRAM with 590 Gbps random access bandwidth and large noise margin, IEICE ELECTRONICS EXPRESS, 4(2), 21-25, 20070125
  97. Realization of K-Nearest-Matches search capability in fully-parallel associative memories, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A(6), 1240-1243, 200706
  98. Acceleration of DCT processing with massive-parallel memory-embedded SIMD matrix processor, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(8), 1312-1315, 200708
  99. 4-port unified data/instruction cache design with distributed crossbar and interleaved cache-line words, IEICE TRANSACTIONS ON ELECTRONICS, E90C(11), 2157-2160, 200711
  100. Mixed digital-analog associative memory enabling fully-parallel nearest Euclidean distance search, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(4B), 2231-2237, 2007
  101. Realization of K-Nearest-Matches search capability in fully-parallel associative memories, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A(6), 1240-1243, 2007
  102. Scalable FPGA/ASIC implementation architecture for parallel table-lookup-coding using multi-ported content addressable memory, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 346-354, 2007
  103. A 2-stage-pipelined 16 port SRAM with 590 Gbps random access bandwidth and large noise margin, IEICE ELECTRONICS EXPRESS, 4(2), 21-25, 2007
  104. Acceleration of DCT processing with massive-parallel memory-embedded SIMD matrix processor, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(8), 1312-1315, 2007
  105. 4-port unified data/instruction cache design with distributed crossbar and interleaved cache-line words, IEICE TRANSACTIONS ON ELECTRONICS, E90C(11), 2157-2160, 2007
  106. A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC, IEICE Trans. on Electronics, E89-C(11), 1612-1619, 20061101
  107. Performance Evaluation of Superscalar Processor with Multi-Bank Register File and an Implementation Result, WSEAS Transactions on Computer, 9(5), 1993-2000, 20060901
  108. Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video Segmentation, IEICE Trans. on Information & Systems, E89-D(3), 1299-1302, 20060301
  109. Evaluation of Bank based Multi-port Memory Architecture with Blocking Network, Wiley, Systems & Computers in Japan, 37(2), 22-33, 20060201
  110. Huffman Encoding Architecture with Self-Optimizing Performance and Multiple CAM-Match Utilization, CA2.3, 20061101
  111. Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline, 1299-1302, 20061201
  112. Application of Multi-ported CAM for Parallel Coding, 1681-1684, 20061201
  113. Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search, 1311-1324, 20061201
  114. Image-Scan Video Segmentation Architecture and FPGA Implementation, 590-591, 20060901
  115. Nearest Euclidean-Distance-Search Associative Memory Architecture with Fully Parallel Mixed Digital-Analog Match Circuitry, 282-283, 20060901
  116. Multi-Bank Register File for Increased Performance of Highly-Parallel Processors, 154-157, 20060901
  117. Performance Evaluation of Superscalar Processor with Multi-Bank Register File Using SPEC2000, Proceedings of the 10th WSEAS International Conference on COMPUTERS, 1062-1067, 20060701
  118. A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA, 2702-2708, 20060701
  119. Minimum Euclidean Distance Associative Memory Architecture with Fully-Parallel Search Capability, 350-354, 20060401
  120. Multi-Object Tracking VLSI Architecture using Image-Scan based Region Growing and Feature Matching, 5575-5578, 20060501
  121. Image Segmentation and Pattern Matching Based FPGA/ASIC Implementation of Real-Time Object Tracking, 176-181, 20060101
  122. Evaluation of bank-based multiport memory architecture with blocking network, ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 89(6), 22-33, 2006
  123. Boundary-active-only adaptive power-reduction scheme for region-growing video-segmentation, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E89D(3), 1299-1302, 200603
  124. A reliability-enhanced TCAM architecture with associated embedded DRAM and ECC, IEICE TRANSACTIONS ON ELECTRONICS, E89C(11), 1612-1619, 200611
  125. A Cost-Efficient High-Performance Dynamic TCAM with Pipelined Hierarchical Searching and Shift Redundancy Architecture, IEEE Journal of Solid-State Circuits, 39, in press, 20050401
  126. A Low-Power Video Segmentation LSI with Boundary-Active-Only Architecture, in press, 20051001
  127. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors, Systems and Computers in Japan, in press, 20050401
  128. Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh, IEICE Trans. on Electronics, E88-C, in press, 20050401
  129. Object Tracking in Video Pictures based on Image Segmentation and Pattern Matching, Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005), in press, 20050501
  130. CAM-based VLSI Architecture for Huffman Coding with Real-time Optimization of the Code Word Table, Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005), in press, 20050601
  131. Design of Superscalar Processor with Multi-Bank Register File, Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005), in press, 20050601
  132. A Cost-Efficient High-Performance Dynamic TCAM With Pipelined Hierarchical Searching and Shift Redundancy Architecture, IEEE Journal of Solid-State Circuits, 40(1), 245-253, 20050101
  133. A Low-Power Video Segmentation LSI with Boundary-Active-Only Architecture, D13-D14, 20050101
  134. Pixel-Parallel Digital-CMOS Implementation of Image-Segmentation by Region Growing, IEE Proc. Circuits, Devices & Systems, 152(12), 579-589, 20051201
  135. Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors, Systems & Computers in Japan, 36(9), 1-13, 20050901
  136. A CAM-based signature-matching co-processor with application-driven power-reduction features, IEICE Trans. on Electronics, E88-C(6), 1332-1342, 20050601
  137. Evaluation of a Bank-based Multi-port Memory Architecture with Blocking Network, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, J88-A(4), 498-510, 20050401
  138. Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh, IEICE Trans. on Electronics, E88-C(4), 622-629, 20050401
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  336. A new global routing algorithm for over-the-cell routing in standard cell layouts, 116-121, 19930901
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  339. Linear and magnetic circular dichroism in the Ce 4d X-ray absorption spectroscopy of CeRh/sub 3/B/sub 2/, Physica B (Netherlands), 186-188, 83-85, 19930401
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  344. Digital Low-Power Real-Time Video Segmentation by Region Growing, 2004, 138-139, 20040915
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  346. Automatic Pattern-Learning Architecture Based on Associative Memory and Short/Long Term Storage Concept, Extended Abstracts of SSDM2004, 2004, 362-363, 20040915
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  350. A Feature Extraction Hardware Design in Computer-Aided Diagnosis System for Colorectal Endoscopic Images with NBI Magnification, 112(237), 13-18, 20121005
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  354. Nearest Neighbor Searching A1gorithms for 2-Dimensional Arrays with Reconfigurable Buses, 49(0), 85-86, 19940920
  355. A Hypergraph k-way Partitioning Method Based on Dynamic Clustering, 49(0), 91-92, 19940920
  356. A Standard Cell Placement Method Based on Circuit Partitioning and Linear Programming, 49(0), 109-110, 19940920
  357. A Fault-Tolerant Leader Election Algorithm in an Anonymous Distributed System, 45(0), 63-64, 19920928
  358. A Distributed Algorithm Simulator for Networks with Arbitrary Topology and Communication Delay Model, 45(0), 279-280, 19920928
  359. A parameter setting method based on superiority of individuals in Genetic Algorithms, 55(0), 463-464, 19970924
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  363. Small-Area Multi-Port Register Files with Multi-Bank Structure, IEICE technical report. Dependable computing, 102(479), 175-180, 20021121
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  370. Mixed Planar and H-V Over-the-Cell Routing for Standard Cells with Nonuniform Over-the-Cell Routing Capacities (Special Issue on Synthesis and Verification of Hardware Design), IEICE transactions on information and systems, 79(10), 1419-1430, 19961025
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  372. C-12-18 Associative-Memory-Based Automatic Learning Architecture for Integrated Recognition Systems, Proceedings of the IEICE General Conference, 2004(2), 20040308
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  375. Evaluation of Compact Multi-bank Memory using Multi-stage Interconnection Network, Technical report of IEICE. ICD, 102(686), 55-60, 20030228
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  377. Access time and Chip area Evaluations of Bank based Multi-port Memory by Memory Generator, Technical report of IEICE. ICD, 104(250), 25-30, 20040812
  378. Pattern-Matching Engine Adaptable to Hamming or Manhattan Distance with Fully-Parallel Processing Capability, Technical report of IEICE. ICD, 102(234), 41-46, 20020718
  379. Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation(Image Processing and Video Processing), IEICE transactions on information and systems, 89(3), 1299-1302, 20060301
  380. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, Technical report of IEICE. ICD, 106(316), 39-44, 20061019
  381. Mixed Analog-Digital Fully-parallel Associative Memory with Differential Amplifier, Technical report of IEICE. ICD, 106(551), 31-36, 20070301
  382. A 128-Kbit, 16-Port SRAM Design with Multi-Stage-Sensing Scheme in 90-nm CMOS Technology, Technical report of IEICE. SDM, 107(194), 149-154, 20070816
  383. Acceleration of AES Encryption with CAM-Enhanced Massive-Parallel SIMD Matrix Processor, IEICE technical report. Computer systems, 107(276), 25-30, 20071018
  384. C-12-10 Associative Memory Design which Realizes Reference-Pattern Learning, Proceedings of the IEICE General Conference, 2007(2), 20070307
  385. C-12-11 Performance Evaluation of Image Segmentation LSI Using Two-Dimensional Block Scanning, Proceedings of the IEICE General Conference, 2007(2), 20070307
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  388. Image Segmentation Algorithm with Parameter Self-Adjustment Considering the Image Characteristic, IEICE technical report. Circuits and systems, 109(199), 77-82, 20090917
  389. Associative-Memory-Based LSI Architecture with Automatic Learning Functionality and Application to Handwritten-Character Recognition, IEICE technical report. Circuits and systems, 109(199), 91-96, 20090917
  390. Efficient Ternary Multiple Search-Operation Architecture based on Flexible Multi-Ported Content Addressable Memory and its Application, IEICE technical report. Circuits and systems, 109(199), 97-102, 20090917
  391. Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories(VLSI Design Technology and CAD), IEICE transactions on fundamentals of electronics, communications and computer sciences, 90(6), 1240-1243, 20070601
  392. Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer(Image Processing and Video Processing), IEICE transactions on information and systems, 90(1), 334-345, 20070101
  393. Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory(Image Processing and Video Processing), IEICE transactions on information and systems, 90(1), 346-354, 20070101
  394. 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words(Integrated Electronics), IEICE transactions on electronics, 90(11), 2157-2160, 20071101
  395. An Improved Face-Detection Method for a Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1, Technical report of IEICE. ICD, 109(336), 83-88, 20091207
  396. Associative-Memory-Based LSI with Adaptive-Learning Capability, Technical report of IEICE. ICD, 109(336), 89-94, 20091207
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  399. The Real-time Feature Extraction Architecture for Colorectal Endoscopic Images with NBI Magnification, IEICE technical report. Computer systems, 113(282), 25-30, 20131101
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  403. Switch Architecture with Banked Multi - port Memory, 2004(12), 37-42, 20040202
  404. Evolution of Non - Numerical Computation performance by Integration of Instruction and Trace Cache, 2003(119), 39-44, 20031127
  405. A Parallel Timing Driven Standard Cell Placement Method with Nonlinear Programming, 1995(119), 163-168, 19951214
  406. Construction and Evaluation of Bank - based Multi - port Memory using Blocking Network, 2003(120), 271-276, 20031127
  407. A Timing - Driven Hierarchical Global Routing Method wih Buffer - Insertion and Wire - Sizing for Multi - Layer ULSI, 1999(12), 105-112, 19990204
  408. A Hardware Algorithm for Graph Bisection, 1994(15), 17-24, 19940204
  409. A Floorplanning Method for Building Block Layout Based on the Manipulation of Topological Constraints, 1992(83), 33-40, 19921022
  410. Path Encoding Method for High Speed Frequency-Mapping Associative Memory, 2011(3), 1-6, 20110511
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  413. Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images, 114(329), 39-44, 20141126
  414. Consideration for Acceleration of Feature Transformation based on the Bag-of-Features for Colorectal Endoscopic Images, 114(302), 7-12, 20141113
  415. An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System, 114(328), 27-32, 20141126
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  417. A Real-Time D-SIFT Feature Extraction for Colorectal Endoscopic Images with NBI Magnification, Proceedings of th1e International Workshop on Nanodevice Technologies 2017, pp. 88-89, March 2, 2017
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  419. A Type Identification Hardware Design in Computer-Aided Diagnosis System for Colorectal Endoscopic Images with NBI Magnification, 112(237), 19-24, 20121005
  420. Multi-Port-Cache Design with Hierarchical Multi-Bank Memory, Technical report of IEICE. VLD, 102(476), 169-174, 20021121
  421. Multi-Port-Cache Design with Hierarchical Multi-Bank Memory, Technical report of IEICE. ICD, 102(477), 169-174, 20021121
  422. Small-Area Multi-Port Register Files with Multi-Bank Structure, Technical report of IEICE. ICD, 102(477), 175-180, 20021121
  423. A Fully-Parallel Associative Memory for Minimum-Manhattan-Distance-Search, Technical report of IEICE. ICD, 102(477), 181-186, 20021121
  424. Construction and Evaluation of Bank-based Multi-port Memory using Blocking Network, Technical report of IEICE. ICD, 103(478), 241-246, 20031121
  425. Mixed Analog-Digital Fully-parallel Associative Memory with Differential Amplifier, Technical report of IEICE. VLD, 106(548), 31-36, 20070301
  426. Massive-Parallel Memory-Embedded SIMD Processor Architecture, IEICE technical report. Nonlinear problems, 109(200), 59-64, 20090917
  427. Analysis of Process Variations by using Ring Oscillator, IEICE technical report. Nonlinear problems, 109(200), 71-76, 20090917
  428. Image Segmentation Algorithm with Parameter Self-Adjustment Considering the Image Characteristic, IEICE technical report. Nonlinear problems, 109(200), 77-82, 20090917
  429. Efficient Ternary Multiple Search-Operation Architecture based on Flexible Multi-Ported Content Addressable Memory and its Application, IEICE technical report. Nonlinear problems, 109(200), 97-102, 20090917
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  434. Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems, IEICE Trans. Inf. & Syst., 94(9), 1742-1754, 20110901
  435. Associative-Memory-Based LSI Architecture with Automatic Learning Functionality and Application to Handwritten-Character Recognition, IEICE technical report, 109(200), 91-96, 20090917
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  440. An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System, Technical report of IEICE. VLD, 114(328), 27-32, 20141126
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  442. Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images, Technical report of IEICE. VLD, 114(328), 39-44, 20141126
  443. An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System, IEICE technical report. Dependable computing, 114(329), 27-32, 20141126
  444. Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification, IEICE technical report. Dependable computing, 114(329), 33-38, 20141126
  445. Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images, IEICE technical report. Dependable computing, 114(329), 39-44, 20141126
  446. Hardware Oriented Speed Traffic-Sign Detection Algorithm for Robust Sign Distortion and Illumination Conditions, IEICE technical report. Computer systems, 114(302), 1-6, 20141113
  447. Consideration for Acceleration of Feature Transformation based on the Bag-of-Features for Colorectal Endoscopic Images, IEICE technical report. Computer systems, 114(302), 7-12, 20141113
  448. A Hierarchical Type Segmentation Algorithm based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images, IEICE technical report. Computer systems, 114(302), 13-18, 20141113
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  455. Memory-based Information Processing Systems, 30(65), 131-136, 20061214
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  462. Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation, IEICE Trans. on Information & Syst., D, 87(2), 500-503, 20040201
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  465. Construction and Evaluation of Band-based Multi-port Memory using Blocking Network, Technical report of IEICE. VLD, 103(476), 241-246, 20031128
  466. Access time and Chip area Evaluations of Bank based Multi-port Memory by Memory Generator, Technical report of IEICE. SDM, 104(248), 25-30, 20040812
  467. Evaluation of a Bank Based Multi-port Memory Architecture with Blocking Network, The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese edition) A, 88(4), 498-510, 20050401
  468. A 4.5Mb Dynamic TCAM with Pipelined Hierarchical Searching and Shift Redundancy Architecture, Technical report of IEICE. ICD, 104(24), 7-12, 20040416
  469. Banked Multiport Register File for Highly Parallel Processors, Technical report of IEICE. ICD, 104(521), 13-18, 20041216
  470. Evaluation of Branch Predictor for Unified Instruction Trace Cache, IPSJ SIG Notes, 2005(120), 75-80, 20051130
  471. A Chip for Real-Time Segmentation Processing with Object-based Image-Scan Architecture, IEICE technical report, 106(425), 73-78, 20061207
  472. Memory-based Information Processing Systems, IEICE technical report, 106(425), 131-136, 20061207
  473. A 128-Kbit, 16-Port SRAM Design with Multi-Stage-Sensing Scheme in 90-nm CMOS Technology, IEICE technical report, 107(195), 149-154, 20070816
  474. Acceleration of Multimedia Data Processing with CAM-Enhanced Massive-Parallel SIMD Matrix Processor, IEICE technical report, 107(276), 19-24, 20071018
  475. C-12-9 Implementation Method of Advanced Encryption Standard (AES) with Super Parallel SIMD Processor, Proceedings of the IEICE General Conference, 2007(2), 20070307
  476. C-12-20 An Efficient Implementation of Scan-Based Image Segmentation Architecture, Proceedings of the IEICE General Conference, 2008(2), 20080305
  477. C-12-27 Stability Evaluation of SRAM-cells in Small-Scale CMOS Technology, Proceedings of the IEICE General Conference, 2008(2), 20080305
  478. C-12-32 Implementation of AES Processing on Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1, Proceedings of the Society Conference of IEICE, 12, 2008
  479. C-12-31 A Parallel Face Detection on Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1 (2), Proceedings of the Society Conference of IEICE, 12, 2008
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  482. Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor, IEICE Trans. Inf. & Syst., D, 90(8), 1312-1315, 20070801
  483. Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture, Jpn J Appl Phys, 48(4), 04C078-04C078-4, 20090425
  484. A computer system to be used with laser-based endoscopy for quantitative diagnosis of early gastric cancer., Journal of clinical gastroenterology, 49(2), 2015
  485. Corrigendum to "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" [Artif. Intell. Med. 68 (March 2016) 1-16]., Artificial intelligence in medicine, 72, 2016
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  488. An Integrated Method for Virtual Path Topology Design and Bandwidth Allocation Considering Multiple QoS Classes in ATM Networks, 1997(1), 161-168, 19970221
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  490. An Adaptive Genetic Algorithm with Sequence - Pair Representation of Solutions for VLSI Floorplanning, 1999(101), 119-126, 19991126
  491. A Hierarchical Buffer Block Planning Method for ULSI Floorplanning, 2001(117), 51-56, 20011128
  492. A Timing - Driven Standard - Cell Placement Method Based on Cell - Clustering and the New Placement Model, 2001(117), 57-62, 20011128
  493. A RISC Processor DLX-GA with Instruction Set Suitable for High-speed Execution of a Genetic Algorithm, Transactions of Information Processing Society of Japan, 44(2), 340-343, 20030215
  494. A Timing - driven Pin Assignment Algorithm with Improvement of Cell Placement in Standard Cell Layout, Transactions of Information Processing Society of Japan, 40(4), 1606-1617, 19990415
  495. An LSI Implementation of a Genetic Algorithm with Adaptive Selection of Crossover Operators, Transactions of Information Processing Society of Japan, 41(6), 1766-1776, 20000615
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  497. The proposal of integrted trace cache which combined instruction cache and trace cache, IPSJ SIG Notes, 2003(27), 79-84, 20030310
  498. A RISC Processor DLX - GA with Instruction Set Suitable for High - Speed Execution of a Genetic Algorithm, IPSJ SIG Notes, 2001(10), 65-70, 20010126
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  501. A Formal Logic Verification Method Based on Circuit Partitioning Considering BDD Size, IPSJ SIG Notes, 1993(111), 47-54, 19931216
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  503. A Circuit Partitioning Method Considering Performance and Physical Constraints for Multi - Chip Module Layout Design, IPSJ SIG Notes, 1995(6), 129-136, 19950119
  504. A Parallel Timing Driven Standard Cell Placement Method with Nonlinear Programming, IPSJ SIG Notes, 1995(119), 163-168, 19951214
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  507. A Rectilinear Steiner Tree Construction Algorithm with Simultaneous Buffer Insertion and Wire Sizing, IPSJ SIG Notes, 1998(10), 33-40, 19980130
  508. A Hardware Algorithm for Graph Bisection, IPSJ SIG Notes, 70, 17-24, 1994
  509. A Heuristic Algorithm for Hypergraph Partitioning Based on Dynamic Clustering, IPSJ SIG Notes, 1994(93), 7-12, 19941027
  510. A Timing Driven Standard Cell Global Routing Method, IPSJ SIG Notes, 1994(93), 31-36, 19941027
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  513. A Timing-Driven Hierarchical Global Routing Method with Buffer-Insertion and Wire-Sizing for Multi-Layer ULSI, IPSJ SIG Notes, 99(12), 105-112, 19990204
  514. A Parameter Tuning Method Based on Meta - Heuristics for Genetic Algorithms, IPSJ SIG Notes, 1997(11), 17-24, 19970124
  515. An Adaptive Genetic Algorithm for Parameter Tuning Based on the Superiority of an Individual, IPSJ SIG Notes, 1998(6), 25-30, 19980123
  516. A Fully-Parallel Associative Memory for Minimum-Manhattan-Distance-Search, IEICE technical report. Dependable computing, 102(479), 181-186, 20021121
  517. A Dynamic Thernary CAM in 130nm CMOS Technology With Planar Complementary Capacitors, IEICE technical report. Image engineering, 103(384), 77-82, 20031017
  518. Gray-Scale/Color Image-Segmentation Architecture based on Cell-Network, IEICE technical report. Circuits and systems, 102(162), 49-54, 20020621
  519. Small-Area Multi-Port Register Files due to Bank Structure for Highly Parallel Processors, IEICE technical report. Circuits and systems, 102(163), 31-36, 20020622
  520. Comparison of the Hierarchical and Crossbar-based Architectures for the Construction Multibank Multiport Memory, IEICE technical report. Circuits and systems, 102(163), 37-42, 20020622
  521. A Hardware-Based Genetic Algorithm with Adaptive Selection of Crossover Operators : LSI Implementation and Its Evaluation, IEICE technical report. Computer systems, 97(524), 51-58, 19980130
  522. A Floorplanning Method for Simultaneously Determining Module Placement and Global Routes Considering Buffer Insertion, IEICE technical report. Computer systems, 100(476), 29-34, 20001123
  523. Adapting Genetic Operators and GA Parameters Based on Elite Degree of an Individual in a Genetic Algorithm, The Transactions of the Institute of Electronics,Information and Communication Engineers., 82(9), 1135-1143, 19990925
  524. A Coterie-Based Mutual Exclusion Algorithm for Distributed Systems allowing Multiple Process Failures at Arbitrary Time, The Transactions of the Institute of Electronics,Information and Communication Engineers., 83(8), 823-833, 20000825
  525. A Fault-Tolerant Distributed Mutual Exclusion Algorithm with Arbitrary Failures and Recoveries, IEICE technical report. Theoretical foundations of Computing, 96(398), 41-50, 19961206
  526. Distributed Algorithms for Updating Paths in a Dynamic Network, IEICE technical report. Theoretical foundations of Computing, 93(358), 11-20, 19931126
  527. A Timing-Driven Hierarchical Global Routing Method with Buffer-Insertion and Wire-Sizing for Multi-Layer ULSI, Technical report of IEICE. FTS, 98(585), 63-70, 19990205
  528. A heuristic algorithm for hypergraph partitioning based on dynamic clustering, Technical report of IEICE. FTS, 94(313), 7-12, 19941027
  529. A timing driven standard cell global routing method, Technical report of IEICE. FTS, 94(313), 31-36, 19941027
  530. The Processor IP for Research with Software Development Environment, Technical report of IEICE. FTS, 101(476), 121-126, 20011129
  531. An Integrated Method for Virtual Path Topology Design and Bandwidth Allocation Considering Multiple QoS Classes in ATM Networks, IEICE technical report. Information networks, 96(543), 161-168, 19970221
  532. A performance driven analog module layout generator, IEICE technical report. Circuits and systems, 93(432), 45-52, 19940121
  533. A Graph Bisection Algorithm Based on Subgraph Migration (Special Section on VLSI Design and CAD Algorithms), IEICE transactions on fundamentals of electronics, communications and computer sciences, 77(12), 2039-2044, 19941225
  534. A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout (Special Section on VLSI Design and CAD Algorithms), IEICE transactions on fundamentals of electronics, communications and computer sciences, 77(12), 2053-2057, 19941225
  535. A Performance-Driven Floorplanning Method with Interconnect Performance Estimation, IEICE transactions on fundamentals of electronics, communications and computer sciences, 85(12), 2775-2784, 20021201
  536. An Optimal Channel Pin Assignment Algorithm for Hierarchical Building-Block Layout Design (Special Section on VLSI Design and CAD Algorithms), IEICE transactions on fundamentals of electronics, communications and computer sciences, 76(10), 1636-1644, 19931025
  537. A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout, IEICE transactions on fundamentals of electronics, communications and computer sciences, 81(12), 2476-2484, 19981201
  538. An Adaptive Genetic Algorithm with Sequence-Pair Representation of Solutions for VLSI Floorplanning, IEICE technical report. Computer systems, 99(481), 81-88, 19991127
  539. A Survey on CAD Technologies of System-on-Silicon Era., The Journal of the Institute of Electronics,Information and Communication Engineers, 81(9), 903-907, 199809
  540. VLSI Chip Design and CAD Tools, Proceedings of the IEICE General Conference, 1999, 19990308
  541. A study of compact and multi-banks memory suitable for LSI, Technical report of IEICE. DSP, 102(167), 125-130, 20020620
  542. Gray-Scale/Color Image-Segmentation Architecture based on Cell-Network, Technical report of IEICE. DSP, 102(168), 49-54, 20020621
  543. Small-Area Multi-Port Register Files due to Bank Structure for Highly Parallel Processors, Technical report of IEICE. DSP, 102(169), 31-36, 20020622
  544. Comparison of the Hierarchical and Crossbar-based Architectures for the Construction Multibank Multiport Memory, Technical report of IEICE. DSP, 102(169), 37-42, 20020622
  545. A Dynamic Thernary CAM in 130nm CMOS Technology With Planar Complementary Capacitors, Technical report of IEICE. DSP, 103(380), 77-82, 20031017
  546. A study of compact and multi-banks memory suitable for LSI, Technical report of IEICE. VLD, 102(164), 125-130, 20020620
  547. Gray-Scale/Color Image-Segmentation Architecture based on Cell-Network, Technical report of IEICE. VLD, 102(165), 49-54, 20020621
  548. Small-Area Multi-Port Register Files due to Bank Structure for Highly Parallel Processors, Technical report of IEICE. VLD, 102(166), 31-36, 20020622
  549. Register Access Scheduling Logic for Superscalar Processors with Multi-Bank Register File, Technical report of IEICE. VLD, 102(684), 49-54, 20030228
  550. Evaluation of Compact Multi-bank Memory using Multi-stage Interconnection Network, Technical report of IEICE. VLD, 102(684), 55-60, 20030228
  551. A Hypergraph Partitioning Algorithm Considering Path-Cut Constraints for Circuit Partitioning, Technical report of IEICE. VLD, 96(555), 49-56, 19970306
  552. An MCM Routing Method for Via Minimization Considering Cross talk, Technical report of IEICE. VLD, 93(391), 31-38, 19931216
  553. A formal verification method based on circut partitioning corsidering BDD size, Technical report of IEICE. VLD, 93(391), 47-54, 19931216
  554. A Parallel Timing Driven Standard Cell Placement Method with Nonlinear Programming, Technical report of IEICE. VLD, 95(421), 73-78, 19951215
  555. The Processor IP for Research with Software Development Environment, Technical report of IEICE. VLD, 101(467), 121-126, 20011122
  556. A Parallel Algorithm for Graph Bisection Suitable for VLSI Implementation, The Transactions of the Institute of Electronics,Information and Communication Engineers. A, 78(6), 692-701, 19950625
  557. A Standard Cell Global Routing Algorithm with Net Selection for Over-the Cell Routing, The Transactions of the Institute of Electronics,Information and Communication Engineers. A, 77(12), 1708-1718, 19941201
  558. An Adaptive Method of Selecting Crossover Operators in a Genetic Algorithm, The Transactions of the Institute of Electronics,Information and Communication Engineers., 81(7), 900-909, 199807
  559. Register Access Scheduling Logic for Superscalar Processors with Multi-Bank Register File, Technical report of IEICE. ICD, 102(686), 49-54, 20030228
  560. A Dynamic Thernary CAM in 130nm CMOS Technology With Planar Complementary Capacitors, Technical report of IEICE. ICD, 103(382), 77-82, 20031017
  561. A Hypergraph Partitioning Algorithm Considering Path-Cut Constraints for Circuit Partitioning, Technical report of IEICE. ICD, 96(557), 49-56, 19970306
  562. Architecture for Compact and Fast Associative-Memories with All-Parallel Nearest-Match Hamming-Distance Search, Technical report of IEICE. ICD, 101(1), 27-34, 20010405
  563. The Processor IP for Research with Software Development Environment, Technical report of IEICE. ICD, 101(470), 121-126, 20011122
  564. An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints, IEICE Trans. Fundamentals, A, 83(12), 2569-2576, 20001201
  565. A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC, IEICE transactions on electronics, 89(11), 1612-1619, 20061101
  566. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, 2006(111), 39-44, 20061026
  567. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, IEICE technical report, 106(314), 39-44, 20061019
  568. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, IEICE technical report, 106(318), 39-44, 20061019
  569. Multiple CAM Matches and Self-adapting Codeword Table for Optimized Real-time Huffman Encoding, IEICE technical report, 106(425), 125-130, 20061207
  570. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, 2006(111), 39-44, 20061026
  571. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, IEICE technical report, 106(314), 39-44, 20061019
  572. Super Parallel SIMD Processor with CAM based High-Speed Pattern Matching Capability, IEICE technical report, 106(318), 39-44, 20061019
  573. Parallel Processing of Morphological Pattern Spectrum for a Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1, IEEJ Transactions on Electronics, Information and Systems, 139(3), 237-246, 2019
  574. Root growth detection with a sound wave-based simple measurement method:: Comparison verification with the visualization image of root growth, The Proceedings of the Symposium on Micro-Nano Science and Technology, 2019(0), 2019
  575. Development of growth parameter estimation method about plant micro fluidic system, The Proceedings of the Symposium on Micro-Nano Science and Technology, 2019(0), 2019
  576. Development of mobile fertilization machine with condensed liquid fertilizer, The Proceedings of the Symposium on Micro-Nano Science and Technology, 2019(0), 2019
  577. Real-time Huffman encoder with pipelined CAM-based data path and code-word-table optimizer, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E90D(1), 334-345, 2007
  578. A needle-type micro-sampling device for collecting nanoliter sap sample from plants, ANALYTICAL AND BIOANALYTICAL CHEMISTRY, 2021

Invited Lecture, Oral Presentation, Poster Presentation

  1. An FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images, T. Okamoto, T. Koide, A. T. Hoang, T. Shimizu, K. Sugi, H. Sakurai, T. Tamaki, T. Hirakawa, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, T. Okamoto, T. Koide, A. T. Hoang, T. Shimizu, K. Sugi, H. Sakurai, T. Tamaki, T. Hirakawa, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, the 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016/10/24, Without Invitation, English
  2. Prototype Speed Limit Sign Recognition System Implementation on Rapid Prototyping Platform, A. T. Hoang, T. Okamoto, T. Koide, A. T. Hoang, T. Okamoto, T. Koide, The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016/10/24, Without Invitation, English
  3. A Hardware Accelerator for Bag-of Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2016), 2016/07/10, Without Invitation, English
  4. Compact and High-Speed Hardware Feature Extraction Accelerator for Dense Scale-Invariant Feature Transform, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2016), 2016/07/10, Without Invitation, English
  5. Visual-Word Based Feature Transformation System in Computer Aided Diagnosis for Colorectal Endoscopic Images, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, IEICE ICD, 2016/03/02, Without Invitation, Japanese, IEICE ICD, Higashi-Hiroshima
  6. A Visual-Word Based Feature Transformation System in Computer Aided Diagnosis for Colorectal Endoscopic Images, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, IEICE ICD, 2016/03/02, Without Invitation, Japanese, IEICE ICD, Higashi-Hiroshima
  7. A Type Identification System Based on Support Vector Machine in Computer Aided Diagnosis for Colorectal Endoscopic Images, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, IEICE ICD, 2016/03/02, Without Invitation, Japanese, IEICE ICD, Higashi-Hiroshima
  8. Architecture of Bottom-up Feature Construction for Robust Computer-Aided Diagnosis System, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, 2015/12/01, Without Invitation, Japanese, Nagasaki
  9. Suitable Feature Extraction Architecture for Real-time Computer Aided Diagnosis System on Gastrointestinal Tract, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, 2015/12/01, Without Invitation, Japanese, IEICE RECONF, Nagasaki
  10. Probability Estimation Hardware on SVM for Type Identification of Colorectal Endoscopic Images, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, 2015/12/01, Without Invitation, Japanese
  11. An Implementation of Speed Limit Traffic Sign Recognition System on Rapid Prototyping Platform, H. Sato, T. Koide, A. Hoang, T. Okamoto, H. Sato, T. Koide, A. Hoang, T. Okamoto, 2015/12/01, Without Invitation, Japanese, Nagasaki

Awards

  1. 2016/10/24, Outstanding Paper Award SASIMI2016, General Chair Technical Program Committee Chair
  2. 2003/01, "Asia and South Pachific Design Automation Conference 2003University LSI Design Contest, Special Feature Award", ASP-DAC2003 Univ. LSI Design Contest Com, A Nearest-Hamming-Distance Search Memory With Fully Parallel Mixed Digital-Analog Match Circuitry
  3. 2018/11/10, Young Researchers Poster Award, General Chair, The 2nd International Symposium on Biomedical Engineering, A Hardware Accelerator for Bag-of-Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images
  4. 2017/12/13, The 19th IEEE Hiroshima Branch Student Symposium (HISS) Excellence Research Award, IEEE Hiroshima Chapter, Identification method using CNN features and SVM classification for colonoscopic image real time diagnosis support system

Patented

  1. Patent, 6355908, 2018/06/22
  2. Patent, 3095376, 2018/06/27
  3. Patent, 9959473, 2018/05/01
  4. Patent, 10062161, 2018/08/28

External Funds

Acceptance Results of Competitive Funds

  1. KAKENHI(Grant-in-Aid for Scientific Research (B)), 2017, 2019
  2. KAKENHI, 2016, 2018
  3. Strategic Basic Research Programs(CREST), 2015/12/01, 2018/03/31
  4. Strategic Basic Research Programs(CREST), 2015/12/01, 2019/03/31
  5. Strategic Basic Research Programs(CREST), 2015/12/01, 2020/03/31
  6. KAKENHI, 2014, 2016
  7. Adaptable and Seamless Technology transfer Program through targetdriven R&D, 2013/08/01, 2014/03/31
  8. KAKENHI, 2012, 2014
  9. KAKENHI, Study on a functional memory-based VLSI system to grow and adapt to the environment, 2011, 2013
  10. KAKENHI, Electromagnetic wave propagation for cancer detection, 2009, 2012
  11. KAKENHI, Memory-based VLSI brain research for realizing recognition, learning and decision capability, 2007, 2009
  12. KAKENHI, 2004, 2005
  13. KAKENHI, A 3 Dimensional Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains, 2003, 2007
  14. KAKENHI, A Study on Automatic Layout Design System for Deep-Submicron High-Performance VLSI, 2000, 2001
  15. KAKENHI, 2000, 2001
  16. KAKENHI, A Study on Processor Architecture Dedicated for Adaptive Genetic Algorithms, 2000, 2001
  17. KAKENHI, Fast and small area associative memories with minimum distance search capability, 2000, 2001
  18. KAKENHI, A Study on Hardware Implementation of a Genetic Algorithm with Adaptive Parameter Adjustment, 1998, 1999
  19. KAKENHI, 1998, 1999
  20. KAKENHI, 1996, 1996
  21. KAKENHI, 1994, 1994
  22. KAKENHI, 1994, 1994
  23. KAKENHI, A study on VLSI layout methods based on meta-heuristics, 1993, 1994
  24. KAKENHI, A method for constructing a reliable distributed network system for on-line transaction processing, 1992, 1993
  25. Strategic Basic Research Programs(CREST), 2015/12/01, 2021/03/31
  26. Strategic Basic Research Programs(CREST), 2015/12/01, 2021/03/31

Social Activities

History as Committee Members

  1. TPC Vice Chair of International Conference on Solid State Devices and Materials, 2012, International Conference on Solid State Devices and Materials
  2. TPC Vice Chair of International Conference on Solid State Devices and Materials, 2011, International Conference on Solid State Devices and Materials
  3. TPC Vice Chair of International Conference on Solid State Devices and Materials, 2010, International Conference on Solid State Devices and Materials

Organizing Academic Conferences, etc.

  1. International Symposium on Devices, Circuits and Systems (ISDCS), Technical Program Char, 2019/06, 2019/06
  2. The 3rd Interational Symposium on Biomedical Engineering (ISBE2018), Organizing Committee, 2018/11, 2018/11
  3. International Workshop on Nanodevice Technologies 2018, Organizing Committee, 2018/03, 2018/03
  4. The 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2018), Technical Program Committee, 2018/03, 2018/03
  5. International Workshop on Nanodevice Technologies 2017, Organizing Committee, 2017/03, 2017/03
  6. International Workshop on Nanodevice Technologies 2015, Organizing Committee, 2015/03, 2015/03
  7. International Workshop on Nanodevice Technologies 2013, Organizing Committee, 2013/03, 2013/03
  8. 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013), Organizing Committee, 2013/01, 2013/01
  9. International Conference on Solid State Devices and Materials (SSDM2011), Technical Program Committee Vice Chair (Area 5. Advanced Circuits and System), 2011/09, 2011/09
  10. 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Organizing Committee, 2011/01, 2011/01
  11. International Conference on Solid State Devices and Materials (SSDM2010), Technical Program Committee Vice Chair (Area 5. Advanced Circuits and System), 2010/09, 2010/09