Tetsushi Koide
Last Updated :2025/02/03
- Affiliations, Positions
- Research Institute for Nanodevices, Associate Professor
- Web Site
- E-mail
- koide
hiroshima-u.ac.jp
- Other Contact Details
- "1-4-2, KAGAMIYAMA, HIGASHI-HIROSHIMA, HIROSHIMA, 739-8527, JAPAN", Japan
TEL : (+81)824-24-6265 FAX : (+81)824-24-3499
- Self-introduction
- I am conducting research on medical image (cancer) diagnosis support (CAD) systems, artificial intelligence information integration (LSI) systems, and agricultural support systems using IoT.
If you would like to know about my research project, please search "Tetsushi Koide Hiroshima University" in Google Search Engine
Basic Information
Major Professional Backgrounds
- 2001/05/01, The University of Tokyo, VLSI Design and Education Center (VDEC), Visiting Researcher
- 2004/04/01, Hiroshima University, Department of Semiconductor Electronics and Integration Sciences, Associate Professor
- 2000/04/01, 2001/03/31, Hiroshima University, Faculty of Engineering, Visiting Associate Professor
- 1999/04/01, 2000/03/31, Hiroshima University, Faculty of Engineering, Associate Professor
- 1999/03/01, 1999/03/31, Hiroshima University, Faculty of Engineering, Associate Professor
- 1992/04/01, 1999/02/28, Hiroshima University, the Faculty of Engineering, Research Associate
- 1996/04/01, 1996/10/09, Yuge National College of Maritime Technology, Visiting Assistant Professor
- 2001/04/01, Hiroshima University, Research Center for Nanodevices and Systems, Associate Professor
- 1999/04/01, 2001/03/31, The University of Tokyo, VLSI Design and Education Center (VDEC), Associate Professor
Educational Backgrounds
- Hiroshima University, Graduate School, Division of Engineering, System Engineering, Japan, 1990/04, 1992/03
- Hiroshima University, Faculty of Engineering, Japan, 1986/04, 1990/03
Academic Degrees
- Doctor Engineering, Hiroshima University
- Master of Engineering, Hiroshima University
Educational Activity
- [Bachelor Degree Program] School of Engineering : Cluster 2(Electrical, Electronic and Systems Engineering) : Program of Electronic Devices and Systems
- [Master's Program] Graduate School of Advanced Science and Engineering : Division of Advanced Science and Engineering : Quantum Matter Program
- [Doctoral Program] Graduate School of Advanced Science and Engineering : Division of Advanced Science and Engineering : Quantum Matter Program
In Charge of Primary Major Programs
- Program of Electrical,Systems and Information Engineering
- Electrical, Computer, and Systems Engineering
- Electronic Devices and Systems
Research Fields
- Informatics;Computing Technologies;Computer system
- Informatics;Computing Technologies;High performance computing
- Informatics;Human informatics;Perceptual information processing
- Informatics;Human informatics;Intelligent informatics
- Complex systems;Biomedical engineering;Medical systems
- Complex systems;Biomedical engineering;Biomedical engineering / Biomaterial science and engineering
- Engineering;Electrical and electronic engineering;Electron device / Electronic equipment
- Engineering;Electrical and electronic engineering;Electronic materials / Electric materials
- Engineering;Electrical and electronic engineering;Control engineering / System engineering
- Agricultural sciences;Agroengineering;Agricultural environmental engineering / Agriculturalinformation engineering
- Informatics;Frontiers of informatics;Life / Health / Medical informatics
Research Keywords
- Design Automation|Cache
- Real Time Processing|LSI
- LSI|Image Compression
- Registor File|Image Segmentation
- Digital and Analog Circuits|VLSI
- Vector Quantaization|Image Segmentation
- LSI|Associative Memory
- CAD|Multi-Port Memory
- LSI|Associative Memory
- Learning|Motion Estimation
Affiliated Academic Societies
- Asia and South Pacific Design Automation Conference(ASPDAC'00), 2000
- Asia and South Pacific Design Automation Conference(ASPDAC'01), 2001
- Asia and South Pacific Design Automation Conference(ASPDAC'02)
- Asia and South Pacific Design Automation Conference(ASPDAC'03)
- Asia and South Pacific Design Automation Conference(ASPDAC'04)
- Asia and South Pacific Design Automation Conference(ASPDAC'05), 2004, 2005
- Asia and South Pacific Design Automation Conference(ASPDAC'97), 1996
- Asia and South Pacific Design Automation Conference(ASPDAC'98), 1997
- Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'00), 2000
- Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'01), 2001
- Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'03)
- Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'04)
- Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'06)
- Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), 1997
- Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'98), 1998
- IPSJ, 1994
- IEICE, 1996, 2001
- IEEE
- ACM
Educational Activity
Course in Charge
- 2024, Undergraduate Education, 2Term, CMOS Logic Circuit Design
- 2024, Undergraduate Education, Year, Graduation Thesis
- 2024, Graduate Education (Master's Program) , First Semester, Seminar on Electronics A
- 2024, Graduate Education (Master's Program) , Second Semester, Seminar on Electronics B
- 2024, Graduate Education (Master's Program) , Academic Year, Academic Presentation in Electronics
- 2024, Graduate Education (Master's Program) , Academic Year, Academic Presentation in Electronics
- 2024, Graduate Education (Master's Program) , 1Term, Exercises in Electronics A
- 2024, Graduate Education (Master's Program) , 2Term, Exercises in Electronics A
- 2024, Graduate Education (Master's Program) , 3Term, Exercises in Electronics B
- 2024, Graduate Education (Master's Program) , 4Term, Exercises in Electronics B
- 2024, Graduate Education (Master's Program) , 3Term, System LSI Design Engineering
- 2024, Graduate Education (Master's Program) , Academic Year, Advanced Study in Quantum Matter
- 2024, Graduate Education (Master's Program) , Academic Year, Advanced Study in Quantum Matter
- 2024, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Quantum Matter
Research Activities
Academic Papers
- Parallel Software Encryption of AES Algorithm by Using CAM-Based Massive-Parallel SIMD Matrix Core for Mobile Accelerator, JOURNAL OF ADVANCES IN INFORMATION TECHNOLOGY, 14(2), 355-362, 202304
- Implementation of Floating-Point Arithmetic Processing on Content Addressable Memory-Based Massive-Parallel SIMD matriX Core, IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING, 18(4), 546-558, 202304
- A Method for Diagnosis Support of Colonoscopy Based on NICE Classification Using Deep Learning, Proceedings of the 27th Symposium on Sensing through Image Processing (SSII2021), 1-5, 20210609
- A Method for Diagnosis Support of Colonoscopy Based on JNET Classification Using Deep Learning, Proceedings of the 27th Symposium on Sensing through Image Processing (SSII2021), 1-5, 20210609
- A Method of Sweat Drop Detection Using Deep Learning for Impression Mold Method of Sweat Function Examination, Proceedings of the 27th Symposium on Sensing through Image Processing (SSII2021), 1-6, 20210609
- Automatic Analysis Method of Skinfolds and Furrows Using Deep Learning for Impression Mold Method of Sweat Function Test, Proceedings of the 27th Symposium on Sensing through Image Processing (SSII2021), 1-5, 20210609
- PARALLEL ISOLATION CHANNELS OF SOLUBLE SOLID REAGENTS FOR LONG TERM-USE NUTRIENT ANALYZER, The 25th International Conference on Miniaturized Systems for Chemistry and Life Sciences (microTAS 2021), 1507-1508, 20211010
- Floating-point arithmetic of content addressable memory-based massive-parallel SIMD matrix core, Proc. of RISP International workshop on Nonlinear Circuit, computer and Signal Processing (NCSP), 20210301
- Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model, IEEE ELECTRON DEVICE LETTERS, 30(8), 873-875, 200908
- Measurement-Based Ring Oscillator Variation Analysis, IEEE DESIGN & TEST OF COMPUTERS, 27(5), 6-13, 2010
- An associative memory-based learning model with an efficient hardware implementation in FPGA, EXPERT SYSTEMS WITH APPLICATIONS, 38(4), 3499-3513, 201104
- Analysis of Within-Die Complementary Metal-Oxide-Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM, JAPANESE JOURNAL OF APPLIED PHYSICS, 50(4), 201104
- Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E94D(9), 1742-1754, 201109
- A Scalable Massively Parallel Processor for Real-Time Image Processing, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 46(10), 2363-2373, 201110
- An Architecture for Compact Associative Memories with Deca-ns Nearest-Match Capability up to Large Distances, 170-171, 20010201
- ★, Compact associative-memory architecture with fully-parallel search capability for the minimum Hamming distance, IEEE Journal of Solid-State Circuits, 37(2), 218-227, 20020201
- A RISC Architecture for high-speed execution of genetic algorithms, Proc. 2001 Genetic and Evolutionary Computation Conference=, 1338-1345, 20010701
- A parallel genetic algorithm with adaptive adjustment of genetic parameters, Proc. 2001 Genetic and Evolutionary Computation Conference=, 679-686, 20010701
- A performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion, Proc. of the Tenth Workshop on Synthesis And System Integration of MIxed Technologies, 226-233, 20011001
- An iterative improvement circuit partitioning algorithm under path delay constraints, IEICE Transactions on Fundamentals of Electronics= Communications and Computer Sciences, E83-A(12), 2569-2576, 20001201
- Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 99-104, 20000101
- ★, Genetic algorithm accelerator GAA-II, Proc. of Asia and South Pacific Design Automation Conference 2000, 9-10, 20000101
- An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 3, 65-68, 20000501
- An architecture for compact associative memories with deca-ns nearest-match capability up to large distances, 2001 IEEE International Solid-State Circuits Conference (ISSCC 2001)= Dig. of Tech. Paper, 44, 170-171, 20010201
- A timing-driven global routing with pin assignment, block reshaping, and positioning for building block layout, IEICE Transactions on Fundamentals of Electronics= Communications and Computer Sciences, E81-A(12), 2476-2484, 19981201
- A timing-driven floorplanning algorithm with the Elmore delay model for building block layout, INTEGRATION= the VLSI journal, 27(1), 57-76, 19990101
- GAA : A VLSI genetic algorithm accelerator with on-the-fly adaptation of crossover operations, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 2, 268-271, 19980501
- Adapting parameters based on pedigree of individuals in a genetic algorithm, Proc. of the Symposium on Genetic Algorithms, 510-517, 19980701
- A circuit partitioning algorithm under path delay constraints, Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, WT32-1.1, 113-116, 19981101
- A performance-driven global routing algorithm with wire-sizing and buffer-insertion, WT32-3.1, 121-124, 19981101
- Solving the rectangular problem by an adaptive GA based on sequence-pair, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 181-184, 19990101
- An LSI implementation of an adaptive genetic algorithm with on-the-fly crossover operator selection, 37-40, 19990101
- A timing-driven floorplanning algorithm with the Elmore delay model for building block layout, 403-414, 19970801
- Timing-driven pin assignment with improvement of cell placement in standard cell layout, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 3, 1552-1555, 19970601
- ★, On-the-fly crossover adaptation of genetic algorithm, Proc. of Genetic Algorithms in Engineering Systems : Innovations and Applications, 197-202, 19970901
- A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 577-583, 19980201
- Solving the capacitor placement problem in a radial distribution system using an adaptive genetic algorithm, Proc. of the 5th International Conference on Parallel Problem Solving From Nature, 1028-1037, 19980301
- Mixed planar and H-V over-the-cell routing for standard cells with nonuniform over-the-cell routing capacities, IEICE Transactions on Information and Systems, E79-D(10), 1419-1430, 19961001
- An efficient timing-driven global routing method for standard cell layout, IEICE Transactions on Information and Systems, E79-D(10), 1410-1418, 19961001
- ★, Pin assignment with global routing for VLSI building block layout, IEEE Trans. on Computer-Aided Design on Integrated Circuits and Systems, 15(12), 1575-1583, 19961201
- A timing-driven placement algorithm with the Elmore delay model for row based VLSIs, INTEGRATION= the VLSI journal, 24(1), 53-77, 19970101
- A timing-driven global routing algorithm considering channel density minimization for standard cell layout, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 4, 424-427, 19960501
- An optimal pin assignment algorithm with improvement of cell placement in standard cell layout, Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, 381-384, 19961101
- Par-POPINS: A timing driven parallel placement method with the Elmore delay model for row based VLSIs, Proc. of Asia and South Pacific Design Automation Conference, 133-140, 19970101
- A standard cell global routing algorithm with net selection for over-the-cell routing, Electronics and Communication in Japan part2, 78(12), 102-115, 19951201
- A three-layer over-the-cell multi-channel router for a new cell model, INTEGRATION= the VLSI journal, 21(3), 171-189, 19960301
- A verification algorithm for logic circuits with internal variables, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 1920-1921, 19950401
- An MCM routing algorithm considering crosstalk, Proc. of 1995 IEEE International Symposium on Circuits and Systems, 211-214, 19950401
- A new system partitioning method under performance and physical constraints for multi-chip modules, Proc. of Asia and South Pacific Design Automation Conference, 119-126, 19950801
- ★, A new performance driven placement method with the Elmore delay model for row based VLSIs, Proc. of Asia and South Pacific Design Automation Conference, 405-412, 19950801
- A three-layer over-the-cell multi-channel routing method for a new cell model, Proc. of Asia and South Pacific Design Automation Conference, 195-202, 19950801
- A floorplanning method with topological constraint manipulation in VLSI building block layout, IEICE Transactions on Fundamentals of Electronics= Communications and Computer Sciences, E77-A(12), 2053-2057, 19941201
- A graph bisection algorithm based on subgraph migration, IEICE Transactions on Fundamentals of Electronics= Communications and Computer Sciences, E77-A(12), 2039-2044, 19941201
- A floorplanning method with topological constraint manipulation, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 1, 165-168, 19940501
- Three-layer channel routing for standard cells with column-dependent variable over-the-cell routing capacities, Proc. of 1994 IEEE Custom Integrated Circuits Conference, 28.1.1-28.1.4, 19940501
- A systolic graph partitioning algorithm for VLSI design, Proc. of 1994 IEEE International Symposium on Circuits and Systems, 1, 225-228, 19940501
- An optimal channel pin assignment algorithm for hierarchical building-block layout design, IEICE Trans. on Fundamentals of Electronics= Communications and Computer Science, E76-A(10), 1636-1644, 19931001
- Gate array placement based on mincut partitioning with path delay constraints, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 2059-2062, 19930501
- A new global routing algorithm for over-the-cell routing in standard cell layouts, Proc. of European Design Automation Conference, 116-121, 19930901
- Optimal channel pin assignment with multiple intervals for building block layout, Proc. of European Design Automation Conference, 348-353, 19920901
- An integrated approach to pin assignment and global routing for VLSI building-block layout, Proc. of European Conference on Design Automation, 24-28, 19930201
- A performance-driven ?oorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion, Proc. Synthesis and System Integration of Mixed Technologies 2001, 226-233, 20010101
- A RISC processor for high-speed execution of genetic algorithms, Proc. 2001 Genetic and Evolutionary Computation Conference, 1338-1345, 20010701
- A parallel genetic algorithm with adaptive adjustment of genetic parameters, Proc. 2001 Genetic and Evolutionary Computation Conference, 679-686, 20010701
- An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints, IEICE Trans. Fundamentals, E83-A(12), 2569-2576, 20001201
- An adaptive genetic algorithm for VLSI ?oorplanning based on sequence-pair, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 65-68, 20000501
- Genetic algorithm accelerator GAA-II, Proc. 2000 Asia-South Paci?c Design Automation Conference, 9-10, 20000101
- Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer, Proc. 2000 Asia-South Paci?c Design Automation Conference, 99-104, 20000101
- A timing-driven ?oorplanning algorithm with the Elmore delay model for building block layout, INTEGRATION= the VLSI journal, 27, 57-76, 19990101
- An LSI implementation of an adaptive genetic algorithm with on-the-?y crossover operator selection, Proc. 2000 Asia-South Paci?c Design Automation Conference, 37-40, 19990101
- Solving the rectangular packing problem by an adaptive GA based on sequence pair, Proc. 2000 Asia-South Paci?c Design Automation Conference, 181-184, 19990101
- A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout, IEICE Trans. Fundamentals, E81-A(12), 2476-2484, 19981201
- A performance-driven global routing algorithm with wire-sizing and buffer-insertion, Proc. 1998 IEEE Asia-Paci?c Conference on Circuits and Systems, 121-124, 19981101
- A circuit partitioning algorithm under path delay constraints, Proc. 1998 IEEE Asia-Paci?c Conference on Circuits and Systems, 113-116, 19981101
- Solving the capacitor placement problem in a radial distribution system using an adaptive genetic algorithm, Proceedings of the 5-th Conference on Parallel Problem Solving from Nature, 510-517, 19980901
- Adapting parameters based on pedigree of individuals in a genetic algorithm, Proceedings of the Third Annual Genetic Programming Conference, 510-517, 19980701
- GAA: A VLSI genetic algorithm accelerator with on-the-?y adaptation of crossover operators, 2, 268-271, 19980501
- A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout, Proceedings of the Asia-South Pacific Design Automation Conference, 577-583, 19980101
- On-the-?y crossover adaptation of genetic algorithms, 197-202, 19970901
- A timing-driven ?oorplanning algorithm with the Elmore delay model for building block layout, 403-414, 19970801
- Timing-driven pin assignment with improvement of cell placement in standard cell layout, Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, 1552-1555, 19970601
- A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs, INTEGRATION= the VLSI journal, 24(1), 53-77, 19970101
- Pin assignment with global routing for VLSI building block layout, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 15(12), 1575-1583, 19961201
- An optimal pin assignment algorithm with improvement of cell placement in standard cell layout, Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, 381-384, 19961101
- A timing-driven global routing algorithm considering channel density minimization for standard cell layout, Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, 424-427, 19960501
- A three-layer over-the-cell multi-channel router for a new cell model, INTEGRATION= the VLSI journal, 21(3), 171-189, 19960101
- Mixed planar and H-V over-the-cell routing for standard cells with nonuniform over-thecell routing capacities, E79-D(10), 1419-1430, 19960101
- An effcient timing-driven global routing method for standard cell layout, E79-D(10), 1410-1418, 19960101
- A new performance driven placement method with the Elmore delay model for row based VLSIs, Proceedings of the Asia-South Paci?c Design Automation Conference, 405-412, 19950801
- A three-layer over-the-cell multi-channel routing method for a new cell model, Proceedings of the Asia-South Paci?c Design Automation Conference, 195-202, 19950801
- A new system partitioning method under performance and physical constraints for multichip modules, Proceedings of the Asia-South Paci?c Design Automation Conference, 119-126, 19950801
- A veri?cation algorithm for logic circuits with internal variables, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 1920-1923, 19950401
- An MCM routing algorithm considering crosstalk, Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, 211-214, 19950401
- A graph bisection algorithm based on subgraph migration, IEICE Trans. Fundamentals, E77-A(12), 2039-2044, 19941201
- A systolic graph partitioning algorithm for VLSI design, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, 225-228, 19940501
- A ?oorplanning method with topological constraint manipulation, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, 165-168, 19940501
- Three-layer channel routing for standard cells with column-dependent variable over-the-cell routing capacities, Proceedings of the IEEE 1994 Custom Integrated Circuits Conference, 643-646, 19940501
- An optimal channel pin assignment algorithm for hierarchical building-block layout design, IEICE Trans. Fundamentals, E76-A(10), 1636-1644, 19930101
- A new global routing algorithm for over-the-cell routing in standard cell layouts, 116-121, 19930901
- Gate array placement based on mincut partitioning with path delay constraints, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 2059-2062, 19930501
- An integrated approach to pin assignment and global routing for VLSI building-block layout, Proceedings of the European Conference on Design Automation with the European Event in ASIC Design, 24-28, 19930201
- An optimal channel pin assignment with multiple intervals for building block layout, 348-353, 19920901
- A Performance-Driven Floorplanning Method with Interconnect Performance Estimation, IEICE Transactions on Fundametals of Electronics= Communications and Computer Sciences, E85-A(12), 2775-2784, 20021201
- Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance, Proc. of 2002 Symposium on VLSI Circuits, 252-255, 20020601
- Digital gray-scale/color image-segmentation architecture for cell-network-based real-time applications, Proc. of The 2002 International Technical Conference On Circuits/Systems= Computers and Communications (ITC-CSCC2003), 670-673, 20020701
- Real-time segmentation architecture of gray-scale/color motion pictures and digital test-chip implementation, Proc. of the 2002 IEEE Asia-Pacific Conference on ASICs (AP-ASIC2002), 237-240, 20020801
- Low-complexity, highly-parallel color motion-picture segmentation architecture for compact digital CMOS implementation, 1994 International Conf. on Solid State Devices and Materials, 242-243, 20020901
- Fully parallel nearest Manhattan-distance-search memory with large reference-pattern number, Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (SSDM2002), 254-255, 20020901
- A nearest-Hamming-distance search memory with fully parallel mixed digital-analog match circuitry, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 591-592, 20030101
- Optimized Bank-Based Multi-Port Memories through a Hierarchical Multi-Bank Structure, Proc. of the 11th Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI 2003), 323-330, 20030401
- High Access Bandwidth Multi-Port-Cache Design with Compact Hierarchical 1-Port-Bank Structure, Proc. of the 11th Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI 2003), 394-400, 20030401
- An Associative Memory for Real-Time Applications Requiring Fully Parallel Nearest Manhattan-Distance-Search, Proc. of the 11th Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI 2003), 200-205, 20030401
- A High-speed and Low Power Hierarchical Multi-Port Cache, Proc. of the 6th International Symposium on low-power and high-speed chip (COOL Chips VI), in press, 20030401
- CMOS Test Chip for a High-Speed Digital Image-Segmentation Architecture with Pixel-Parallel Processing, Proc. of The 2002 International Technical Conference On Circuits/Systems= Computers and Communications (ITC-CSCC2003), in press, 20030701
- A Novel Hierarchical Multi-port Cache, Proc. of ESSCIRC2003, in press, 20030901
- Compact Associative-Memory Architecture with Fully-Parallel Search Capability for the Minimum Hamming Distance, IEEE Journal of Solid-State Circuits, 37(2), 218-227, 20020201
- Fully-Parallel Pattern-Matching Engine with Dynamic Adaptability to Hamming or Manhattan Distance, 1999 Symposium on VLSI Circuits Dig. of Technical Papers, 252-255, 20020601
- Digital Gray-Scale/Color Image-Segmentation Architecture for Cell-Network-Based Real-Time Applications, Proc. 1996 International Technical Conference on Circuits/Systems= Computers and Communications(ITC-CSCC), 670-673, 20020601
- Real-Time Segmentation Architecture of Gray-Scale/Color Motion Pictures and Digital Test-Chip Implementation, Proc. of the 2002 IEEE Asia-Pacific Conference on ASICs (AP-ASIC2002), 237-240, 20020701
- Low-Complexity, Highly-Parallel Color Motion-Picture Segmentation Architecture for Compact Digital CMOS Implementation, 1994 International Conf. on Solid State Devices and Materials, 242-243, 20020901
- Fully Parallel Nearest Manhattan-Distance-Search Memory with Large Reference-Pattern Number, 254-255, 20020901
- A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), 591-592, 20030101
- An Associative Memory for Real-Time Applications Requiring Fully-Parallel Nearest Manhattan-Distance Search, 200-205, 20030401
- Optimized Bank-Based Multi-Port Memories through a Hierarchical Multi-Bank Structure, 323-330, 20030401
- High Access Bandwidth Multi-Port-Cache Design with Compact Hierarchical 1-Port-Bank Structure, 394-400, 20030401
- High-Speed and Low-Power Multi-Port-Cache, Proceedings of COOL Chips VI, 76, 20030501
- A Novel Hierarchical Multi-Port Cache, in press, 20030901
- Low-Power Real-Time Region-Growing Image-Segmentation in 0.35mm CMOS due to Subdivided-Image and Boundary-Active-Only Architectures, 146-147, 20030901
- Combined Data/Instruction Cache with Bank-Based Multi-Port Architecture, Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials (SSDM2003), 150-151, 20030901
- A Hierarchical 512-Kbit SRAM with 8 Ports in 130nm CMOS, Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials (SSDM2003), 152-153, 20030901
- Associative Memory with Fully Parallel Nearest-Manhattan-Distance Search for Low-Power Real-Time Single-Chip Applications, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC2001), in press, 20040101
- Bank-Type Multiport Register File for Highly-Parallel Processors, Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials (SSDM2003), 400-401, 20030901
- 350nm CMOS Test-Chip for Architecture Verification of Real-Time QVGA Color-Video Segmentation at the 90nm Technology Node, Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC2004), in press, 20040101
- Compact 12-Port Multi-Bank Register File Test-Chip in 0.35um CMOS for Highly Parallel Processors, Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC2004), in press, 20040101
- A 143MHz, 1.1W, 32mm2, 4.5Mb dynamic ternary CAM in 130nm embedded DRAM technology with pipelined hierarchical searching and row/column-shift redundancy architecture, 2004 IEEE International Solid-State Circuits Conference (ISSCC 2004)= Dig. of Tech. Paper, 208-209, 20040201
- Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessor, The INSTITUTE of ELECTRONICS= INFORMATION AND COMMUNICATION ENGINEERS., in press, 20040401
- Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation, IEICE Transactions on Information and Systems, in press, 20040401
- Analog-Circuit-Component Optimization with Genetic Algorithm, The 2004 IEEE International Midwest Symposium on Circuits and Systems, 1, 489-492, 20040401
- Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors, J87-D-I(3), 350-363, 20040301
- Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation, E87-D(2), 500-503, 20040201
- Distributed versus centralized crossbar function for realizing bank-based multiport memories, IEE Electronics Letters, 40(2), 101-1-3, 20040101
- Distributed-crossbar architecture for area-efficient combined data/instruction caches with multiple ports, IEE Electronics Letters, 40(3), 160-162, 20040201
- A Cost-Efficient High-Performance Dynamic TCAM with Pipelined Hierarchical Searching and Shift Redundancy Architecture, IEEE Journal of Solid-State Circuits, 39, in press, 20050401
- A Cost-Efficient Dynamic Ternary CAM in 130nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture, 1999 Symposium on VLSI Circuits Dig. of Technical Papers, 83-84, 20040601
- Proposition and Evaluation of a Bank-Based Multi-Port Memory with Blocking Network, Proceedings of the 2004 International Technical Conference on Circuits/Systems= Computers and Communications (ITC-CSCC2004), 6C2L-3-1-6C2L-3-4, 20040701
- Low-Power Design for Real-Time Image Segmentation LSI and Compact Digital CMOS Implementation, Proceedings of the 2004 IEEE Asia-Pacific Conference on ASICs (AP-ASIC2004), 432-433, 20040801
- Low Power Bank-based Multi-port SRAM Design due to Bank Standby Mode, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, 1, 569-572, 20040701
- Reference-Pattern Learning and Optimization from an Input-Pattern Stream for Associative-Memory-Based Pattern-Recognition System, Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2004), 1, 561-564, 20040701
- Optimized Multi-Stage Minimum-Distance-Search Circuit with Feedback Stabilization for Fully-Parallel Associative Memories, Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2004), 1, 161-164, 20040701
- Analog-Circuit-Component Optimization with Genetic Algorithm, Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2004), 1, 489-492, 20040701
- A Hierarchical Placement Method for Standard Cell Layout Based on Wire Length Driven Clustering, Proceedings of the 2004 IEEE International Midwest Symposium on Circuits and Systems, III, 423-426, 20040701
- Digital Low-Power Real-Time Video Segmentation by Region Growing, 1994 International Conf. on Solid State Devices and Materials, 138-139, 20040901
- Automatic Pattern-Learning Architecture Based on Associative Memory and Short/Long Term Storage Concept, Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials (SSDM2004), 362-363, 20040901
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- A FLOORPLANNING METHOD WITH TOPOLOGICAL CONSTRAINT MANIPULATION IN VLSI BUILDING-BLOCK LAYOUT, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E77A(12), 2053-2057, 1994
- A standard cell global routing algorithm with net selection for over-the-cell routing, ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 78(12), 102-115, 1995
- A three-layer over-the-cell multi-channel router for a new cell model, INTEGRATION-THE VLSI JOURNAL, 21(3), 171-189, 1996
- Pin assignment with global routing for VLSI building block layout, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 15(12), 1575-1583, 1996
- An efficient timing-driven global routing method for standard cell layout, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E79D(10), 1410-1418, 1996
- Mixed planar and H-V over-the-cell routing for standard cells with nonuniform over-the-cell routing capacities, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E79D(10), 1419-1430, 1996
- Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 37(2), 218-227, 2002
- A performance-driven floorplanning method with interconnect performance estimation, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E85A(12), 2775-2784, 2002
- Efficient video-picture segmentation algorithm for cell-network-based digital CMOS implementation, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E87D(2), 500-503, 2004
- A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 40(1), 245-253, 2005
- Boundary-active-only adaptive power-reduction scheme for region-growing video-segmentation, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E89D(3), 1299-1302, 2006
- Memory Effect and Fast Spinodal Decomposition, 20070828
- Shock propagation and stability in causal dissipative hydrodynamics, 20080512
- Stability and Causality in relativistic dissipative hydrodynamics, 20080719
- Extensivity of Irreversible Current and Stability in Causal Dissipative
Hydrodynamics, 20090126
- Shear viscosity coefficient and relaxation time of causal dissipative
hydrodynamics in QCD, 20090630
- A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E81A(12), 2476-2484, 1998
- Effect of bulk viscosity on Elliptic Flow near QCD phase transition, 20091010
- Extended Thermodynamic Relation and Fluctuation Theorem in Stochastic
Dynamics with Time Reversed Process, 20090720
- Bulk viscosity effects on elliptic flow, 20090930
- The effect of shear and bulk viscosities on elliptic flow, 20100211
- Dissipative relativistic fluid dynamics: a new way to derive the
equations of motion from kinetic theory, 20100428
- Schroedinger Equation in Rotating Frame by using Stochastic Variational
Method, 20161122
- More quantum centrifugal effect in rotating frame, 20170505
- Uncertainty relation for angle from a quantum-hydrodynamical perspective, 20200316
- Dynamical Correlations as Origin of Nonextensive Entropy, 20050616
- How Far Can the SO(10) Two Higgs Model Describe the Observed Neutrino
Masses and Mixings ?, 20020223
- Incorporating Memory Effects in Phase Separation Processes, 20060315
- Open Problems in Hydrodynamical Approach to Relativistic Heavy Ion
Collisions, 20060614
- Relativistic Dissipative Hydrodynamics: A Minimal Causal Theory, 20070322
- New Formulation of Causal Dissipative Hydrodynamics: Shock wave
propagation, 20070119
- Decay process accelerated by tunneling in its very early stage, 20021025
- A timing-driven floorplanning algorithm with the Elmore delay model for building block layout, INTEGRATION-THE VLSI JOURNAL, 27(1), 57-76, 1999
- Distributed against centralised crossbar function for realising bank-based multiport memories, ELECTRONICS LETTERS, 40(2), 101-103, 2004
- Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports, ELECTRONICS LETTERS, 40(3), 160-162, 2004
- Embedded low-power dynamic TCAM architecture with transparently scheduled refresh, IEICE TRANSACTIONS ON ELECTRONICS, E88C(4), 622-629, 2005
- A CAM-based signature-matching co-processor with application-driven power-reduction features, IEICE TRANSACTIONS ON ELECTRONICS, E88C(6), 1332-1342, 2005
- Pixel-parallel digital CMOS implementation of image segmentation by region growing, IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 152(6), 579-589, 2005
- Evaluation of bank-based multiport memory architecture with blocking network, ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 89(6), 22-33, 2006
- Computer-aided diagnosis of colorectal polyp histology by using a real-time image recognition system and narrow-band imaging magnifying colonoscopy, GASTROINTESTINAL ENDOSCOPY, 83(3), 643-649, 2016
- Development of multi-class computer-aided diagnostic systems using the NICE/JNET classifications for colorectal lesions, Journal of Gastroenterology and Hepatology (Australia), 37(1), 104-110, 20220101
- Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual, Systems and Computers in Japan, 32(1), 29-37, 20010101
- A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time, Systems and Computers in Japan, 33(12), 87-96, 20021115
Publications such as books
- 2022/02/22, AgriBio, In order to understand how the environment around the crop and the application of fertilizer to the crop affect the changes in crop traits, we have developed a technique and instrumentation to acquire time-series image information of the crop and extract parameters related to the trait changes from them. This enables us to obtain information on trait changes in each part of the crop, to examine the relationship with fertilizer application and environmental conditions, and to identify quantifiable parameters. We also developed the basic technology to automatically extract and track the quantitative values of the parameters representing the trait changes from various images, such as visual and thermographic images., In order to understand how the environment around the crop and the application of fertilizer to the crop affect the changes in crop traits, we have developed a technique and instrumentation to acquire time-series image information of the crop and extract parameters related to the trait changes from them. This enables us to obtain information on trait changes in each part of the crop, to examine the relationship with fertilizer application and environmental conditions, and to identify quantifiable parameters. We also developed the basic technology to automatically extract and track the quantitative values of the parameters representing the trait changes from various images, such as visual and thermographic images., Development of image processing technology and sensors for understanding the growth status of crops, Crop growth monitoring, image processing technology, sensors, AI, Hokuryukan & NEW SCIENCE co., ltd, 2022, 2022, Scholarly Book, Contributor, 日本語, Tetsushi Koide, 01327-03, 98, 13-17
- 2021/11/30, Biomedical Engineering, Chapter 16, A Hierarchical Type Segmentation Hardware for Colorectal Endoscopic Images with Narrow Band Imaging Magnification, A Hierarchical Type Segmentation Hardware for Colorectal Endoscopic Images with Narrow Band Imaging Magnification, A Hierarchical Type Segmentation Hardware for Colorectal Endoscopic Images with Narrow Band Imaging Magnification, A Hierarchical Type Segmentation Hardware for Colorectal Endoscopic Images with Narrow Band Imaging Magnification, Biomedical Engineering, AI, Image Processing, VLSI, Hardware, Jenny Stanford Publishing Pte Ltd., 2021, 2021, Scholarly Book, Contributor, English, Tetsushi Koide, Toru Tamaki, Shigeto Yoshida, Shinji Tanaka, 978-9814877633, 380, 319-329
Invited Lecture, Oral Presentation, Poster Presentation
- An FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images, T. Okamoto, T. Koide, A. T. Hoang, T. Shimizu, K. Sugi, H. Sakurai, T. Tamaki, T. Hirakawa, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, T. Okamoto, T. Koide, A. T. Hoang, T. Shimizu, K. Sugi, H. Sakurai, T. Tamaki, T. Hirakawa, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, the 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016/10/24, Without Invitation, English
- Prototype Speed Limit Sign Recognition System Implementation on Rapid Prototyping Platform, A. T. Hoang, T. Okamoto, T. Koide, A. T. Hoang, T. Okamoto, T. Koide, The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016/10/24, Without Invitation, English
- A Hardware Accelerator for Bag-of Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2016), 2016/07/10, Without Invitation, English
- Compact and High-Speed Hardware Feature Extraction Accelerator for Dense Scale-Invariant Feature Transform, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, T. Koide, T. Okamoto, T. Shimizu, K. Sugi, A. T. Hoang, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno and S. Tanaka, The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2016), 2016/07/10, Without Invitation, English
- Visual-Word Based Feature Transformation System in Computer Aided Diagnosis for Colorectal Endoscopic Images, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, IEICE ICD, 2016/03/02, Without Invitation, Japanese, IEICE ICD, Higashi-Hiroshima
- A Visual-Word Based Feature Transformation System in Computer Aided Diagnosis for Colorectal Endoscopic Images, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, IEICE ICD, 2016/03/02, Without Invitation, Japanese, IEICE ICD, Higashi-Hiroshima
- A Type Identification System Based on Support Vector Machine in Computer Aided Diagnosis for Colorectal Endoscopic Images, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, IEICE ICD, 2016/03/02, Without Invitation, Japanese, IEICE ICD, Higashi-Hiroshima
- Architecture of Bottom-up Feature Construction for Robust Computer-Aided Diagnosis System, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, K. Sugi, T. Koide, T. Shimizu, T. Okamoto, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, 2015/12/01, Without Invitation, Japanese, Nagasaki
- Suitable Feature Extraction Architecture for Real-time Computer Aided Diagnosis System on Gastrointestinal Tract, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, T. Shimizu, T. Koide, A. Hoang, K. Sugi, T. Okamoto, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Yoshida, H. Mieno, S. Tanaka, 2015/12/01, Without Invitation, Japanese, IEICE RECONF, Nagasaki
- Probability Estimation Hardware on SVM for Type Identification of Colorectal Endoscopic Images, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, T. Okamoto, T. Koide, T. Shimizu, K. Sugi, A. Hoang, H. Sato, T. Tamaki, B. Raytchev, K. Kaneda, S. Toshida, H. Mieno, S. Tanaka, 2015/12/01, Without Invitation, Japanese
- An Implementation of Speed Limit Traffic Sign Recognition System on Rapid Prototyping Platform, H. Sato, T. Koide, A. Hoang, T. Okamoto, H. Sato, T. Koide, A. Hoang, T. Okamoto, 2015/12/01, Without Invitation, Japanese, Nagasaki
Awards
- 2022/07/06, The 36thInternational Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2021), Best Paper Award, President of IEIE, Automatic Detection of Skin Surface Structure Using Deep Learning for the Impression Mold Technique
- 2016/10/24, Outstanding Paper Award
SASIMI2016, General Chair
Technical Program Committee Chair
- 2003/01, "Asia and South Pachific Design Automation Conference 2003University LSI Design Contest, Special Feature Award", ASP-DAC2003 Univ. LSI Design Contest Com, A Nearest-Hamming-Distance Search Memory With Fully Parallel Mixed Digital-Analog Match Circuitry
- 2018/11/10, Young Researchers Poster Award, General Chair, The 2nd International Symposium on Biomedical Engineering, A Hardware Accelerator for Bag-of-Features based Visual Word Transformation in Computer Aided Diagnosis for Colorectal Endoscopic Images
- 2017/12/13, The 19th IEEE Hiroshima Branch Student Symposium (HISS) Excellence Research Award, IEEE Hiroshima Chapter, Identification method using CNN features and SVM classification for colonoscopic image real time diagnosis support system
Patented
- Patent, 10062161, 2018/08/28
- Patent, 3095376, 2018/06/27
- Patent, 6355908, 2018/06/22
- Patent, 9959473, 2018/05/01
External Funds
Acceptance Results of Competitive Funds
- 2021
- KAKENHI(Grant-in-Aid for Scientific Research (B)), 2017, 2019
- KAKENHI, 2016, 2018
- Strategic Basic Research Programs(CREST), 2015/12/01, 2018/03/31
- Strategic Basic Research Programs(CREST), 2015/12/01, 2019/03/31
- Strategic Basic Research Programs(CREST), 2015/12/01, 2020/03/31
- KAKENHI, 2014, 2016
- Adaptable and Seamless Technology transfer Program through targetdriven R&D, 2013/08/01, 2014/03/31
- KAKENHI, 2012, 2014
- KAKENHI, Study on a functional memory-based VLSI system to grow and adapt to the environment, 2011, 2013
- KAKENHI, Electromagnetic wave propagation for cancer detection, 2009, 2012
- KAKENHI, Memory-based VLSI brain research for realizing recognition, learning and decision capability, 2007, 2009
- KAKENHI, 2004, 2005
- KAKENHI, A 3 Dimensional Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains, 2003, 2007
- KAKENHI, A Study on Automatic Layout Design System for Deep-Submicron High-Performance VLSI, 2000, 2001
- KAKENHI, 2000, 2001
- KAKENHI, A Study on Processor Architecture Dedicated for Adaptive Genetic Algorithms, 2000, 2001
- KAKENHI, Fast and small area associative memories with minimum distance search capability, 2000, 2001
- KAKENHI, A Study on Hardware Implementation of a Genetic Algorithm with Adaptive Parameter Adjustment, 1998, 1999
- KAKENHI, 1998, 1999
- KAKENHI, 1996, 1996
- KAKENHI, 1994, 1994
- KAKENHI, 1994, 1994
- KAKENHI, A study on VLSI layout methods based on meta-heuristics, 1993, 1994
- KAKENHI, A method for constructing a reliable distributed network system for on-line transaction processing, 1992, 1993
- Strategic Basic Research Programs(CREST), 2015/12/01, 2021/03/31
- Strategic Basic Research Programs(CREST), 2015/12/01, 2021/03/31
- Strategic Basic Research Programs(CREST), 2015/12/01, 2021/03/31
- KAKENHI(Grant-in-Aid for Scientific Research (B)), 2020, 2022
Social Activities
History as Committee Members
- TPC Vice Chair of International Conference on Solid State Devices and Materials, 2012, International Conference on Solid State Devices and Materials
- TPC Vice Chair of International Conference on Solid State Devices and Materials, 2011, International Conference on Solid State Devices and Materials
- TPC Vice Chair of International Conference on Solid State Devices and Materials, 2010, International Conference on Solid State Devices and Materials
Organizing Academic Conferences, etc.
- International Symposium on Devices, Circuits and Systems (ISDCS), Technical Program Char, 2019/06, 2019/06
- The 3rd Interational Symposium on Biomedical Engineering (ISBE2018), Organizing Committee, 2018/11, 2018/11
- International Workshop on Nanodevice Technologies 2018, Organizing Committee, 2018/03, 2018/03
- The 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2018), Technical Program Committee, 2018/03, 2018/03
- International Workshop on Nanodevice Technologies 2017, Organizing Committee, 2017/03, 2017/03
- International Workshop on Nanodevice Technologies 2015, Organizing Committee, 2015/03, 2015/03
- International Workshop on Nanodevice Technologies 2013, Organizing Committee, 2013/03, 2013/03
- 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013), Organizing Committee, 2013/01, 2013/01
- International Conference on Solid State Devices and Materials (SSDM2011), Technical Program Committee Vice Chair (Area 5. Advanced Circuits and System), 2011/09, 2011/09
- 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Organizing Committee, 2011/01, 2011/01
- International Conference on Solid State Devices and Materials (SSDM2010), Technical Program Committee Vice Chair (Area 5. Advanced Circuits and System), 2010/09, 2010/09