Mamoru Sasaki

Last Updated :2021/04/06

Affiliations, Positions
Graduate School of Advanced Science and Engineering, Associate Professor

Basic Information

Academic Degrees

  • Ph.D., Kumamoto University

Research Fields

  • Engineering;Electrical and electronic engineering;Electron device / Electronic equipment

Research Keywords

  • high-speed I/O
  • carrierless communication
  • CDMA
  • IC test
  • High-speed wireless communiction system
  • high-speed sirial communiation

Educational Activity

Course in Charge

  1. 2021, Undergraduate Education, 4Term, CMOS Integrated Design
  2. 2021, Undergraduate Education, 1Term, Electric and Electronic Measurements
  3. 2021, Graduate Education (Master's Program) , First Semester, Seminar on Electronics A
  4. 2021, Graduate Education (Master's Program) , Second Semester, Seminar on Electronics B
  5. 2021, Graduate Education (Master's Program) , Academic Year, Academic Presentation in Electronics
  6. 2021, Graduate Education (Master's Program) , 1Term, Exercises in Electronics A
  7. 2021, Graduate Education (Master's Program) , 2Term, Exercises in Electronics A
  8. 2021, Graduate Education (Master's Program) , 3Term, Exercises in Electronics B
  9. 2021, Graduate Education (Master's Program) , 4Term, Exercises in Electronics B
  10. 2021, Graduate Education (Master's Program) , 3Term, Electromagnetism for RF and High-speed Circuit Design
  11. 2021, Graduate Education (Master's Program) , Academic Year, Advanced Study in Quantum Matter
  12. 2021, Graduate Education (Doctoral Program) , Academic Year, Advanced Study in Quantum Matter

Research Activities

Academic Papers

  1. A maximum and minimum circuit with multiple inputs in current mode, Trans. IEICE Japan, Vol.E70(No.4), 392-395, 19870401
  2. Synthesis of fuzzy membership function circuits with multiple inputs and their applications, Trans. IEICE Japan, Vol.E71(No.1), 77-87, 19880101
  3. Fuzzy multiple-input maximum and minimum circuits in current mode and their analyses using bounded-difference equations, IEEE Trans. on Computers, Vol.39(No.6), 768-774, 19900601
  4. An implementation of multiple-valued logic and fuzzy logic circuits using 1.5V Bi-CMOS current-mode circuit, Trans. IEICE Japan, Vol.E76-D(No.5), 571-576, 19930501
  5. Boltzmann Machine processor using single-bit operation, Trans. IEICE Japan, Vol.E76-A(No.6), 878-885, 19930601
  6. 7.5MFLIPS fuzzy microprocessor using SIMD and Logic-in-Memory structure, Trans. IEICE Japan, Vol.E77-C(No.7), 1075-1082, 19940701
  7. 1V supply voltage Bi-CMOS current mode circuits and their application to ADC, Trans. IEICE Japan, Vol.E78-A(No.3), 395-402, 19950301
  8. Fully balanced CMOS current-mode filters for high-frequency applications, Trans. IEICE Japan, Vol.E79-A(No.6), 836-844, 19960601
  9. A Boltmann Machine with Non-rejective Move, Trans. IEICE Japan, Vol.E85-A(No.6), 1229-1235, 20020601
  10. A 1V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique, IEICE Trans. Electron., E89-C, 769-774, 20060601
  11. A 0.6V Supply CMOS Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization, JJAP, VOL.46(NO.4B), 2252-2256, 20070401
  12. Low-Voltage, Low-Phase-Noise Ring-VCO using 1/f-noise Reduction Techniques, JJAP, VOL.46(NO.4B), 2257-2260, 20070401
  13. 2Gbps CMOS amplitude-shift-keying demodulator with input sensitivity of 33dBm, 2010 European Microwave Conference (EuMC), 268-271, 20101001
  14. Magnetic circular dichroism in the soft X-ray absorption spectra of intercalation compounds FexTiS2, PHYSICA E, 10(1-3), 387-390, 200112
  15. A new type of quantized Hall effect in layered semiconductors Bi2-xSnxTe3 and Sb2-xSnxTe3, PHYSICA B, 298(1-4), 510-514, 200104
  16. Anomalous quantum Hall effect in charge-density-wave material eta-Mo4O11, PHYSICA B, 298(1-4), 520-524, 200104
  17. Possible mechanism of a new type of three-dimensional quantized Hall effect in layered semiconductors Bi2-xSnxTe3, JOURNAL OF LOW TEMPERATURE PHYSICS, 123(3-4), 219-238, 200112
  18. A 2.7 Gcps and 7-multiplexing CDMA serial communication chip using two-step synchronization technique, IEICE TRANSACTIONS ON ELECTRONICS, E88C(6), 1233-1240, 200506
  19. A 1V low-noise CMOS amplifier using autozeroing and chopper stabilization technique, IEICE TRANSACTIONS ON ELECTRONICS, E89C(6), 769-774, 200606
  20. Analysis of transmission characteristics of Gaussian monocycle pulses for silicon integrated antennas, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 45(4B), 3272-3278, 200604
  21. Design of a millimeter-wave CMOS radiation oscillator with an above-chip patch antenna, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 53(10), 1128-1132, 200610
  22. 0.6V Supply complementary metal oxide semiconductor amplifier using noise reduction technique of autozeroing and chopper stabilization, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(4B), 2252-2256, 200704
  23. Low-voltage, low-phase-noise ring voltage-controlled oscillator using 1/f-noise reduction techniques, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 46(4B), 2257-2260, 200704
  24. 20GHz uniform-phase uniform-amplitude standing-wave clock distribution, IEICE ELECTRONICS EXPRESS, 3(2), 11-16, 20060125
  25. Low-voltage and low-noise CMOS analog circuits using scaled devices, IEICE TRANSACTIONS ON ELECTRONICS, E90C(6), 1149-1155, 200706
  26. Principal component analysis-based object detection/recognition chip for wireless interconnected three-dimensional integration, JAPANESE JOURNAL OF APPLIED PHYSICS, 47(4), 2746-2748, 200804
  27. A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 44(10), 2800-2807, 200910